diff options
| author | Martin Roth <martin.roth@amd.com> | 2023-01-09 21:21:48 -0700 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-01-17 16:08:18 +0000 |
| commit | b486fe95bf455008d5d5c6df7e1c1fc836e9ccd1 (patch) | |
| tree | c319d32e6a64cf914ad8ac5ebdc80f716fc12a76 /src/soc/amd/glinda/Makefile.inc | |
| parent | 3f5985972d8893614671c81dfec1e915f09e1d1f (diff) | |
soc/amd: Use fixed EFS location for Phoenix & Glinda
The AMD SoCs no longer have a variable position for EFS - it's now fixed
at 0xff020000 - 128KiB into the 16MiB ROM decode region.
It's a little more complex than that because the chip can be larger than
16MiB, and the entire ROM can be decoded if mapped above the 4GiB
boundary, but we don't currently support doing that in coreboot, so this
is enough for now.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I343a875ba9aa8294a090f2eff7b5dfb5e86334f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/amd/glinda/Makefile.inc')
| -rw-r--r-- | src/soc/amd/glinda/Makefile.inc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 3e50011523..e65f92442c 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -67,10 +67,8 @@ MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) $(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) -GLINDA_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +# Fixed EFS location +GLINDA_FWM_POSITION=0xff020000 # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough |