diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2024-03-18 21:08:25 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-03-22 21:49:41 +0000 |
| commit | 4b187551d202039189c2f81b56836409c002f23d (patch) | |
| tree | 79c6302dd471e4a0daadca5039fed275fb444e2e /src/soc/amd/genoa_poc | |
| parent | 15784f1b03ee3bdcea180efd9bf47168aa452ddb (diff) | |
vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chip
Move the gpp_bridge_* device functions that are bridges to the external
PCIe ports below the corresponding mpio chip. This avoids the need for
dummy devices and does things in a slightly more coreboot-native way.
TEST=PCIe lane config reported by openSIL is identical
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/genoa_poc')
| -rw-r--r-- | src/soc/amd/genoa_poc/chipset.cb | 320 |
1 files changed, 240 insertions, 80 deletions
diff --git a/src/soc/amd/genoa_poc/chipset.cb b/src/soc/amd/genoa_poc/chipset.cb index dccffde822..92dcb5df96 100644 --- a/src/soc/amd/genoa_poc/chipset.cb +++ b/src/soc/amd/genoa_poc/chipset.cb @@ -16,36 +16,80 @@ chip soc/amd/genoa_poc device pci 00.3 alias rcec_0 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_0_0_a off end - device pci 01.2 alias gpp_bridge_0_1_a off end - device pci 01.3 alias gpp_bridge_0_2_a off end - device pci 01.4 alias gpp_bridge_0_3_a off end - device pci 01.5 alias gpp_bridge_0_4_a off end - device pci 01.6 alias gpp_bridge_0_5_a off end - device pci 01.7 alias gpp_bridge_0_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_0_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_0_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_0_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_0_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_0_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_0_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_0_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_0_7_a off end - device pci 02.2 alias gpp_bridge_0_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_0_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_0_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_0_0_b off end - device pci 03.2 alias gpp_bridge_0_1_b off end - device pci 03.3 alias gpp_bridge_0_2_b off end - device pci 03.4 alias gpp_bridge_0_3_b off end - device pci 03.5 alias gpp_bridge_0_4_b off end - device pci 03.6 alias gpp_bridge_0_5_b off end - device pci 03.7 alias gpp_bridge_0_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_0_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_0_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_0_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_0_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_0_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_0_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_0_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_0_7_b off end - device pci 04.2 alias gpp_bridge_0_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_0_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_0_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable - device pci 05.1 alias gpp_bridge_0_0_c off end - device pci 05.2 alias gpp_bridge_0_1_c off end - device pci 05.3 alias gpp_bridge_0_2_c off end - device pci 05.4 alias gpp_bridge_0_3_c off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.1 alias gpp_bridge_0_0_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.2 alias gpp_bridge_0_1_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.3 alias gpp_bridge_0_2_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.4 alias gpp_bridge_0_3_c off end + end device pci 07.0 on end # Dummy device function, do not disable device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0 @@ -84,30 +128,66 @@ chip soc/amd/genoa_poc device pci 00.3 alias rcec_1 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_1_0_a off end - device pci 01.2 alias gpp_bridge_1_1_a off end - device pci 01.3 alias gpp_bridge_1_2_a off end - device pci 01.4 alias gpp_bridge_1_3_a off end - device pci 01.5 alias gpp_bridge_1_4_a off end - device pci 01.6 alias gpp_bridge_1_5_a off end - device pci 01.7 alias gpp_bridge_1_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_1_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_1_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_1_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_1_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_1_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_1_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_1_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_1_7_a off end - device pci 02.2 alias gpp_bridge_1_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_1_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_1_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_1_0_b off end - device pci 03.2 alias gpp_bridge_1_1_b off end - device pci 03.3 alias gpp_bridge_1_2_b off end - device pci 03.4 alias gpp_bridge_1_3_b off end - device pci 03.5 alias gpp_bridge_1_4_b off end - device pci 03.6 alias gpp_bridge_1_5_b off end - device pci 03.7 alias gpp_bridge_1_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_1_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_1_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_1_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_1_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_1_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_1_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_1_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_1_7_b off end - device pci 04.2 alias gpp_bridge_1_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_1_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_1_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable @@ -127,30 +207,66 @@ chip soc/amd/genoa_poc device pci 00.3 alias rcec_2 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_2_0_a off end - device pci 01.2 alias gpp_bridge_2_1_a off end - device pci 01.3 alias gpp_bridge_2_2_a off end - device pci 01.4 alias gpp_bridge_2_3_a off end - device pci 01.5 alias gpp_bridge_2_4_a off end - device pci 01.6 alias gpp_bridge_2_5_a off end - device pci 01.7 alias gpp_bridge_2_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_2_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_2_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_2_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_2_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_2_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_2_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_2_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_2_7_a off end - device pci 02.2 alias gpp_bridge_2_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_2_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_2_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_2_0_b off end - device pci 03.2 alias gpp_bridge_2_1_b off end - device pci 03.3 alias gpp_bridge_2_2_b off end - device pci 03.4 alias gpp_bridge_2_3_b off end - device pci 03.5 alias gpp_bridge_2_4_b off end - device pci 03.6 alias gpp_bridge_2_5_b off end - device pci 03.7 alias gpp_bridge_2_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_2_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_2_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_2_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_2_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_2_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_2_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_2_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_2_7_b off end - device pci 04.2 alias gpp_bridge_2_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_2_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_2_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable @@ -170,36 +286,80 @@ chip soc/amd/genoa_poc device pci 00.3 alias rcec_3 off end device pci 01.0 on end # Dummy device function, do not disable - device pci 01.1 alias gpp_bridge_3_0_a off end - device pci 01.2 alias gpp_bridge_3_1_a off end - device pci 01.3 alias gpp_bridge_3_2_a off end - device pci 01.4 alias gpp_bridge_3_3_a off end - device pci 01.5 alias gpp_bridge_3_4_a off end - device pci 01.6 alias gpp_bridge_3_5_a off end - device pci 01.7 alias gpp_bridge_3_6_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.1 alias gpp_bridge_3_0_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.2 alias gpp_bridge_3_1_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.3 alias gpp_bridge_3_2_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.4 alias gpp_bridge_3_3_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.5 alias gpp_bridge_3_4_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.6 alias gpp_bridge_3_5_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 01.7 alias gpp_bridge_3_6_a off end + end device pci 02.0 on end # Dummy device function, do not disable - device pci 02.1 alias gpp_bridge_3_7_a off end - device pci 02.2 alias gpp_bridge_3_8_a off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.1 alias gpp_bridge_3_7_a off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 02.2 alias gpp_bridge_3_8_a off end + end device pci 03.0 on end # Dummy device function, do not disable - device pci 03.1 alias gpp_bridge_3_0_b off end - device pci 03.2 alias gpp_bridge_3_1_b off end - device pci 03.3 alias gpp_bridge_3_2_b off end - device pci 03.4 alias gpp_bridge_3_3_b off end - device pci 03.5 alias gpp_bridge_3_4_b off end - device pci 03.6 alias gpp_bridge_3_5_b off end - device pci 03.7 alias gpp_bridge_3_6_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.1 alias gpp_bridge_3_0_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.2 alias gpp_bridge_3_1_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.3 alias gpp_bridge_3_2_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.4 alias gpp_bridge_3_3_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.5 alias gpp_bridge_3_4_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.6 alias gpp_bridge_3_5_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 03.7 alias gpp_bridge_3_6_b off end + end device pci 04.0 on end # Dummy device function, do not disable - device pci 04.1 alias gpp_bridge_3_7_b off end - device pci 04.2 alias gpp_bridge_3_8_b off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.1 alias gpp_bridge_3_7_b off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 04.2 alias gpp_bridge_3_8_b off end + end device pci 05.0 on end # Dummy device function, do not disable - device pci 05.1 alias gpp_bridge_3_0_c off end - device pci 05.2 alias gpp_bridge_3_1_c off end - device pci 05.3 alias gpp_bridge_3_2_c off end - device pci 05.4 alias gpp_bridge_3_3_c off end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.1 alias gpp_bridge_3_0_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.2 alias gpp_bridge_3_1_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.3 alias gpp_bridge_3_2_c off end + end + chip vendorcode/amd/opensil/genoa_poc/mpio + device pci 05.4 alias gpp_bridge_3_3_c off end + end device pci 07.0 on end # Dummy device function, do not disable device pci 07.1 alias gpp_bridge_3_a off |