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authorArthur Heymans <arthur@aheymans.xyz>2023-07-13 14:11:18 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-09-28 16:32:13 +0000
commitb4aaa6f0ab0a729a7638899140a1cdd0c800cb8a (patch)
tree8c341774e7acdc86ea1255c1f24f6c62e47ed29b /src/soc/amd/genoa
parent2c749ef1a4b1d9bd18a5d08a9df517ca1127b2a7 (diff)
soc/amd/genoa/reset.c: Add reset methods
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ifb4d7dda5fcf1ccacb901b24e4f7cf6945ee16e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76503 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/genoa')
-rw-r--r--src/soc/amd/genoa/Makefile.inc1
-rw-r--r--src/soc/amd/genoa/reset.c27
2 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc
index 56a98e6b48..efbd3b1275 100644
--- a/src/soc/amd/genoa/Makefile.inc
+++ b/src/soc/amd/genoa/Makefile.inc
@@ -2,6 +2,7 @@
ifeq ($(CONFIG_SOC_AMD_GENOA),y)
all-y += mmap_boot.c
+all-y += reset.c
all-y += config.c
bootblock-y += early_fch.c
diff --git a/src/soc/amd/genoa/reset.c b/src/soc/amd/genoa/reset.c
new file mode 100644
index 0000000000..ac0c981718
--- /dev/null
+++ b/src/soc/amd/genoa/reset.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <cf9_reset.h>
+#include <reset.h>
+#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/reset.h>
+
+void do_cold_reset(void)
+{
+ /* De-assert and then assert all PwrGood signals on CF9 reset. */
+ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
+ TOGGLE_ALL_PWR_GOOD);
+ outb(RST_CPU | SYS_RST, RST_CNT);
+}
+
+void do_warm_reset(void)
+{
+ /* Warm resets are not supported and must be executed as cold */
+ do_cold_reset();
+}
+
+void do_board_reset(void)
+{
+ do_cold_reset();
+}