diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-20 16:31:31 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-22 15:03:17 +0000 |
| commit | d26f5a103fe300dc345b8059394039fa22d1e442 (patch) | |
| tree | b970e8dc4d69b88b7cd317ec65557ffbca2f1af9 /src/soc/amd/genoa/include | |
| parent | 943a2c90d827ede0ae64f1518d39a381c69ff698 (diff) | |
soc/amd/genoa: add I2C support
The Genoa SoC has 6 I2C controllers. In order to support those, select
SOC_AMD_COMMON_BLOCK_I2C and implement the SoC-specific functions and
data structures needed by the common AMD I2C code. Since the common AMD
I2C code also reports if the controller is enabled or not in the SSDT,
change the corresponding DSDT code to use this information. In this
patch the I2C pad control registers don't get configured by coreboot yet
and we rely on ABL already having those set up correctly which seems to
be an assumption that the reference firmware is making too. PPR #55901
Rev 0.26 was used as a reference for the I2C controllers and the GPIO
pins being used.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iebc10de6ea5c6d441cff04e016dcec62405078c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Diffstat (limited to 'src/soc/amd/genoa/include')
| -rw-r--r-- | src/soc/amd/genoa/include/soc/i2c.h | 36 | ||||
| -rw-r--r-- | src/soc/amd/genoa/include/soc/iomap.h | 4 |
2 files changed, 40 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/include/soc/i2c.h b/src/soc/amd/genoa/include/soc/i2c.h new file mode 100644 index 0000000000..ffff754f1b --- /dev/null +++ b/src/soc/amd/genoa/include/soc/i2c.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_I2C_H +#define AMD_GENOA_I2C_H + +#include <gpio.h> +#include <types.h> + +#define GPIO_I2C0_SCL BIT(0) +#define GPIO_I2C1_SCL BIT(1) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C4_SCL BIT(4) +#define GPIO_I2C5_SCL BIT(5) +#define GPIO_I2C_MASK (GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ + GPIO_I2C2_SCL | GPIO_I2C3_SCL | \ + GPIO_I2C4_SCL | GPIO_I2C5_SCL) + + +#define I2C0_SCL_PIN GPIO_145 +#define I2C1_SCL_PIN GPIO_147 +#define I2C2_SCL_PIN GPIO_149 +#define I2C3_SCL_PIN GPIO_151 +#define I2C4_SCL_PIN GPIO_13 +#define I2C5_SCL_PIN GPIO_19 + +#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx +#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx +#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_149_IOMUX_GPIOxx +#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_151_IOMUX_GPIOxx +#define I2C4_SCL_PIN_IOMUX_GPIOxx GPIO_13_IOMUX_GPIOxx +#define I2C5_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx + +void reset_i2c_peripherals(void); + +#endif /* AMD_GENOA_I2C_H */ diff --git a/src/soc/amd/genoa/include/soc/iomap.h b/src/soc/amd/genoa/include/soc/iomap.h index 5b767e3e27..0e24780a0f 100644 --- a/src/soc/amd/genoa/include/soc/iomap.h +++ b/src/soc/amd/genoa/include/soc/iomap.h @@ -3,6 +3,10 @@ #ifndef AMD_GENOA_IOMAP_H #define AMD_GENOA_IOMAP_H +#define I2C_MASTER_DEV_COUNT 6 +#define I2C_PERIPHERAL_DEV_COUNT 0 +#define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) + #define SPI_BASE_ADDRESS 0xfec10000 /* @Todo : Check these values for Genoa */ |