soc/amd/genoa: rename to genoa_poc

Even though this SoC is called 'Genoa', the openSIL implementation and
the corresponding coreboot integration is only a proof of concept that
isn't fully featured, has known limitations and bugs, and is not meant
for or ready to being productized. Adding the proof of concept suffix to
the name should point this out clearly enough so that no potential
customer could infer that this might be a fully functional and supported
implementation which it is not.

Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

17 files changed, 0 insertions, 1051 deletions

diff --git a/src/soc/amd/genoa/include/soc/acpi.h b/src/soc/amd/genoa/include/soc/acpi.h
deleted file mode 100644
index 5c0efa5868..0000000000
--- a/src/soc/amd/genoa/include/soc/acpi.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef AMD_GENOA_ACPI_H
-#define AMD_GENOA_ACPI_H
-
-#include <acpi/acpi.h>
-#include <device/device.h>
-
-#define ACPI_SCI_IRQ 9
-
-unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
-				    struct acpi_rsdp *rsdp);
-
-#endif /* AMD_GENOA_ACPI_H */
diff --git a/src/soc/amd/genoa/include/soc/amd_pci_int_defs.h b/src/soc/amd/genoa/include/soc/amd_pci_int_defs.h
deleted file mode 100644
index b99ee413b3..0000000000
--- a/src/soc/amd/genoa/include/soc/amd_pci_int_defs.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_AMD_PCI_INT_DEFS_H
-#define AMD_GENOA_AMD_PCI_INT_DEFS_H
-
-/*
- *  * PIRQ and device routing - these define the index into the
- *   * FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
- *    */
-
-#define PIRQ_NC		0x1f	/* Not Used */
-#define PIRQ_A		0x00	/* INT A */
-#define PIRQ_B		0x01	/* INT B */
-#define PIRQ_C		0x02	/* INT C */
-#define PIRQ_D		0x03	/* INT D */
-#define PIRQ_E		0x04	/* INT E */
-#define PIRQ_F		0x05	/* INT F */
-#define PIRQ_G		0x06	/* INT G */
-#define PIRQ_H		0x07	/* INT H */
-#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings */
-#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
-#define PIRQ_HPET_L	0x0a	/* Miscellaneous1 IRQ Settings */
-#define PIRQ_HPET_H	0x0b	/* Miscellaneous2 IRQ Settings */
-#define PIRQ_SIRQA	0x0c	/* Serial IRQ INTA */
-#define PIRQ_SIRQB	0x0d	/* Serial IRQ INTB */
-#define PIRQ_SIRQC	0x0e	/* Serial IRQ INTC */
-#define PIRQ_SIRQD	0x0f	/* Serial IRQ INTD */
-#define PIRQ_SCI	0x10	/* SCI IRQ */
-#define PIRQ_SMBUS	0x11	/* SMBUS0 */
-#define PIRQ_ASF	0x12	/* ASF */
-/* 0x13-0x15 reserved */
-#define PIRQ_PMON	0x16	/* Performance Monitor */
-/* 0x17-0x19 reserved */
-#define PIRQ_SDIO	0x1a	/* SDIO */
-/* 0x1b-0x49 reserved */
-#define PIRQ_GPP0	0x50	/* GPPInt0 */
-#define PIRQ_GPP1	0x51	/* GPPInt1 */
-#define PIRQ_GPP2	0x52	/* GPPInt2 */
-#define PIRQ_GPP3	0x53	/* GPPInt3 */
-/* 0x54-0x59 reserved */
-#define PIRQ_GSCI	0x60	/* SCI Interrupt */
-#define PIRQ_GSMI	0x61	/* SMI Interrupt */
-#define PIRQ_GPIO	0x62	/* GPIO Interrupt */
-/* 0x63-0x6f reserved */
-#define PIRQ_I2C0	0x70	/* I2C0/I3C0 */
-#define PIRQ_I2C1	0x71	/* I2C1/I3C1 */
-#define PIRQ_I2C2	0x72	/* I2C2/I3C2 */
-#define PIRQ_I2C3	0x73	/* I2C3/I3C3 */
-#define PIRQ_UART0	0x74	/* UART0 */
-#define PIRQ_UART1	0x75	/* UART1 */
-#define PIRQ_I2C4	0x76	/* I2C4 */
-#define PIRQ_I2C5	0x77	/* I2C5 */
-#define PIRQ_UART2	0x78	/* UART2 */
-#define PIRQ_UART3	0x79	/* UART3 */
-
-#endif /* AMD_GENOA_AMD_PCI_INT_DEFS_H */
diff --git a/src/soc/amd/genoa/include/soc/aoac_defs.h b/src/soc/amd/genoa/include/soc/aoac_defs.h
deleted file mode 100644
index 90f4de8a3b..0000000000
--- a/src/soc/amd/genoa/include/soc/aoac_defs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_AOAC_DEFS_H
-#define AMD_GENOA_AOAC_DEFS_H
-
-/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
-#define FCH_AOAC_DEV_CLK_GEN		0
-#define FCH_AOAC_DEV_I2C0		5
-#define FCH_AOAC_DEV_I2C1		6
-#define FCH_AOAC_DEV_I2C2		7
-#define FCH_AOAC_DEV_I2C3		8
-#define FCH_AOAC_DEV_I2C4		9
-#define FCH_AOAC_DEV_I2C5		10
-#define FCH_AOAC_DEV_UART0		11
-#define FCH_AOAC_DEV_UART1		12
-#define FCH_AOAC_DEV_UART2		16
-#define FCH_AOAC_DEV_AMBA		17
-#define FCH_AOAC_DEV_ESPI		27
-
-#endif /* AMD_GENOA_AOAC_DEFS_H */
diff --git a/src/soc/amd/genoa/include/soc/cpu.h b/src/soc/amd/genoa/include/soc/cpu.h
deleted file mode 100644
index 836c9877ba..0000000000
--- a/src/soc/amd/genoa/include/soc/cpu.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_CPU_H
-#define AMD_GENOA_CPU_H
-
-#define GENOA_A0_CPUID		CPUID_FROM_FMS(0x19, 0x10, 0)
-#define GENOA_B0_CPUID		CPUID_FROM_FMS(0x19, 0x11, 0)
-
-#endif /* AMD_GENOA_CPU_H */
diff --git a/src/soc/amd/genoa/include/soc/data_fabric.h b/src/soc/amd/genoa/include/soc/data_fabric.h
deleted file mode 100644
index 02c639ab16..0000000000
--- a/src/soc/amd/genoa/include/soc/data_fabric.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_DATA_FABRIC_H
-#define AMD_GENOA_DATA_FABRIC_H
-
-#include <amdblocks/data_fabric_defs.h>
-#include <types.h>
-
-#define DF_VGA_EN			DF_REG_ID(0, 0xc08)
-
-union df_vga_en {
-	struct {
-		uint32_t ve		:  1; /* [ 0.. 0] */
-		uint32_t np		:  1; /* [ 1.. 1] */
-		uint32_t cpu_dis	:  1; /* [ 2.. 2] */
-		uint32_t		:  1; /* [ 3.. 3] */
-		uint32_t dst_fabric_id	: 12; /* [ 4..15] */
-		uint32_t		: 16; /* [16..31] */
-	};
-	uint32_t raw;
-};
-
-#define DF_PCI_CFG_BASE0		DF_REG_ID(0, 0xc80)
-#define DF_PCI_CFG_LIMIT0		DF_REG_ID(0, 0xc84)
-
-#define DF_PCI_CFG_MAP_COUNT		8
-
-#define DF_PCI_CFG_REG_OFFSET(instance)	((instance) * 2 * sizeof(uint32_t))
-#define DF_PCI_CFG_BASE(reg)		(DF_PCI_CFG_BASE0 + DF_PCI_CFG_REG_OFFSET(reg))
-#define DF_PCI_CFG_LIMIT(reg)		(DF_PCI_CFG_LIMIT0 + DF_PCI_CFG_REG_OFFSET(reg))
-
-union df_pci_cfg_base {
-	struct {
-		uint32_t re		: 1; /* [ 0.. 0] */
-		uint32_t we		: 1; /* [ 1.. 1] */
-		uint32_t		: 6; /* [ 2.. 7] */
-		uint32_t segment_num	: 8; /* [ 8..15] */
-		uint32_t bus_num_base	: 8; /* [16..23] */
-		uint32_t		: 8; /* [24..31] */
-	};
-	uint32_t raw;
-};
-
-union df_pci_cfg_limit {
-	struct {
-		uint32_t dst_fabric_id	: 12; /* [ 0..11] */
-		uint32_t		:  4; /* [12..15] */
-		uint32_t bus_num_limit	:  8; /* [16..23] */
-		uint32_t		:  8; /* [24..31] */
-	};
-	uint32_t raw;
-};
-
-#define DF_IO_BASE0			DF_REG_ID(0, 0xd00)
-#define DF_IO_LIMIT0			DF_REG_ID(0, 0xd04)
-
-#define DF_IO_REG_COUNT			8
-
-#define DF_IO_REG_OFFSET(instance)	((instance) * 2 * sizeof(uint32_t))
-#define DF_IO_BASE(reg)			(DF_IO_BASE0 + DF_IO_REG_OFFSET(reg))
-#define DF_IO_LIMIT(reg)		(DF_IO_LIMIT0 + DF_IO_REG_OFFSET(reg))
-
-union df_io_base {
-	struct {
-		uint32_t re		:  1; /* [ 0.. 0] */
-		uint32_t we		:  1; /* [ 1.. 1] */
-		uint32_t		:  3; /* [ 2.. 4] */
-		uint32_t ie		:  1; /* [ 5.. 5] */
-		uint32_t		: 10; /* [ 6..15] */
-		uint32_t io_base	: 13; /* [16..28] */
-		uint32_t		:  3; /* [29..31] */
-	};
-	uint32_t raw;
-};
-
-union df_io_limit {
-	struct {
-		uint32_t dst_fabric_id	: 12; /* [ 0..11] */
-		uint32_t		:  4; /* [12..15] */
-		uint32_t io_limit	: 13; /* [16..28] */
-		uint32_t		:  3; /* [29..31] */
-	};
-	uint32_t raw;
-};
-
-#define DF_IO_ADDR_SHIFT		12
-
-#define DF_MMIO_BASE0			DF_REG_ID(0, 0xd80)
-#define DF_MMIO_LIMIT0			DF_REG_ID(0, 0xd84)
-#define   DF_MMIO_SHIFT			16
-#define DF_MMIO_CTRL0			DF_REG_ID(0, 0xd88)
-#define DF_MMIO_ADDR_EXT0		DF_REG_ID(0, 0xd8c)
-#define   DF_MMIO_EXT_ADDR_SHIFT	48
-
-#define DF_MMIO_REG_SET_SIZE		4
-#define DF_MMIO_REG_SET_COUNT		16
-
-union df_mmio_control {
-	struct {
-		uint32_t re		:  1; /* [ 0.. 0] */
-		uint32_t we		:  1; /* [ 1.. 1] */
-		uint32_t		:  1; /* [ 2.. 2] */
-		uint32_t np		:  1; /* [ 3.. 3] */
-		uint32_t		: 12; /* [ 4..15] */
-		uint32_t dst_fabric_id	: 12; /* [16..27] */
-		uint32_t		:  4; /* [28..31] */
-	};
-	uint32_t raw;
-};
-
-union df_mmio_addr_ext {
-	struct {
-		uint32_t base_ext	: 8; /* [ 0.. 7] */
-		uint32_t		: 8; /* [ 8..15] */
-		uint32_t limit_ext	: 8; /* [16..23] */
-		uint32_t		: 8; /* [24..31] */
-	};
-	uint32_t raw;
-};
-
-#define DF_FICAA_BIOS			DF_REG_ID(4, 0x8C)
-#define DF_FICAD_LO			DF_REG_ID(4, 0xB8)
-#define DF_FICAD_HI			DF_REG_ID(4, 0xBC)
-
-union df_ficaa {
-	struct {
-		uint32_t cfg_inst_acc_en :  1; /* [ 0.. 0] */
-		uint32_t reg_num         : 10; /* [10.. 1] */
-		uint32_t func_num        :  3; /* [13..11] */
-		uint32_t b64_en          :  1; /* [14..14] */
-		uint32_t                 :  1; /* [15..15] */
-		uint32_t inst_id         :  8; /* [23..16] */
-		uint32_t                 :  8; /* [31..24] */
-	};
-	uint32_t raw;
-};
-
-#endif /* AMD_GENOA_DATA_FABRIC_H */
diff --git a/src/soc/amd/genoa/include/soc/gpio.h b/src/soc/amd/genoa/include/soc/gpio.h
deleted file mode 100644
index 72d77c69f9..0000000000
--- a/src/soc/amd/genoa/include/soc/gpio.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_GPIO_H
-#define AMD_GENOA_GPIO_H
-
-#define GPIO_DEVICE_NAME	"AMDI0030"
-#define GPIO_DEVICE_DESC	"GPIO Controller"
-
-#ifndef __ACPI__
-#include <soc/iomap.h>
-#include <amdblocks/gpio.h>
-#endif /* !__ACPI__ */
-
-#include <amdblocks/gpio_defs.h>
-
-/* The following sections describe only the GPIOs defined for this SOC */
-
-#define SOC_GPIO_TOTAL_PINS		267
-
-/* Bank 0: GPIO_0 - GPIO_63 */
-#define GPIO_0				0
-#define GPIO_1				1
-#define GPIO_2				2
-#define GPIO_3				3
-#define GPIO_4				4
-#define GPIO_5				5
-#define GPIO_6				6
-#define GPIO_7				7
-#define GPIO_12				12
-#define GPIO_13				13
-#define GPIO_14				14
-#define GPIO_16				16
-#define GPIO_17				17
-#define GPIO_19				19
-#define GPIO_20				20
-#define GPIO_21				21
-#define GPIO_22				22
-#define GPIO_23				23
-#define GPIO_24				24
-#define GPIO_26				26
-
-/* Bank 1: GPIO_64 - GPIO_127 */
-#define GPIO_74				74
-#define GPIO_75				75
-#define GPIO_76				76
-#define GPIO_86				86
-#define GPIO_87				87
-#define GPIO_88				88
-#define GPIO_89				89
-#define GPIO_104			104
-#define GPIO_105			105
-#define GPIO_106			106
-#define GPIO_107			107
-#define GPIO_108			108
-#define GPIO_109			109
-#define GPIO_110			110
-#define GPIO_115			115
-#define GPIO_116			116
-#define GPIO_117			117
-#define GPIO_118			118
-#define GPIO_119			119
-#define GPIO_120			120
-#define GPIO_121			121
-#define GPIO_122			122
-#define GPIO_123			123
-#define GPIO_124			124
-#define GPIO_125			125
-#define GPIO_126			126
-
-/* Bank 2: GPIO_128 - GPIO_191 */
-#define GPIO_129			129
-#define GPIO_131			131
-#define GPIO_132			132
-#define GPIO_133			133
-#define GPIO_134			134
-#define GPIO_135			135
-#define GPIO_136			136
-#define GPIO_137			137
-#define GPIO_138			138
-#define GPIO_139			139
-#define GPIO_141			141
-#define GPIO_142			142
-#define GPIO_145			145
-#define GPIO_146			146
-#define GPIO_147			147
-#define GPIO_148			148
-#define GPIO_149			149
-#define GPIO_150			150
-#define GPIO_151			151
-#define GPIO_152			152
-
-/* remote GPIO bank: GPIO_256 - GPIO_271 */
-#define GPIO_256			256
-#define GPIO_257			257
-#define GPIO_258			258
-#define GPIO_259			259
-#define GPIO_260			260
-#define GPIO_261			261
-#define GPIO_262			262
-#define GPIO_263			263
-#define GPIO_264			264
-#define GPIO_265			265
-#define GPIO_266			266
-
-/* IOMUX function names and values */
-#define GPIO_0_IOMUX_PWR_BTN_L 0
-#define GPIO_0_IOMUX_GPIO_PU1PD0 1
-#define GPIO_0_IOMUX_GPIOxx 2
-#define GPIO_1_IOMUX_SYS_RESET_L 0
-#define GPIO_1_IOMUX_GPIOxx 1
-#define GPIO_2_IOMUX_WAKE_L 0
-#define GPIO_2_IOMUX_GPIOxx 1
-#define GPIO_3_IOMUX_GPIOxx 0
-#define GPIO_4_IOMUX_GPIOxx 0
-#define GPIO_4_IOMUX_SATA_ACT_L 1
-#define GPIO_5_IOMUX_GPIOxx 0
-#define GPIO_5_IOMUX_DEVSLP0 1
-#define GPIO_6_IOMUX_GPIOxx 0
-#define GPIO_6_IOMUX_DEVSLP1 1
-#define GPIO_7_IOMUX_GPIOxx 0
-#define GPIO_12_IOMUX_PWRGD_OUT 0
-#define GPIO_12_IOMUX_GPIOxx 1
-#define GPIO_13_IOMUX_I2C4_SCL 0
-#define GPIO_13_IOMUX_CLK_48_24_0 1
-#define GPIO_13_IOMUX_GPIOxx 2
-#define GPIO_14_IOMUX_I2C4_SDA 0
-#define GPIO_14_IOMUX_S0A3 1
-#define GPIO_14_IOMUX_GPIOxx 2
-#define GPIO_16_IOMUX_USB_1O_OC_L 0
-#define GPIO_16_IOMUX_GPIOxx 1
-#define GPIO_17_IOMUX_USB11_OC_L 0
-#define GPIO_17_IOMUX_GPIOxx 1
-#define GPIO_19_IOMUX_I2C5_SCL 0
-#define GPIO_19_IOMUX_SMBUS1_SCL 1
-#define GPIO_19_IOMUX_GPIOxx 2
-#define GPIO_20_IOMUX_I2C5_SDA 0
-#define GPIO_20_IOMUX_SMBUS1_SDA 1
-#define GPIO_20_IOMUX_GPIOxx 2
-#define GPIO_21_IOMUX_GPIOxx 0
-#define GPIO_22_IOMUX_GPIOxx 0
-#define GPIO_23_IOMUX_ESPI_RST_OUT_L 0
-#define GPIO_23_IOMUX_GPIOxx 1
-#define GPIO_24_IOMUX_SMERR_L 0
-#define GPIO_24_IOMUX_GPIOxx 1
-#define GPIO_26_IOMUX_PCIE_RST1_L 0
-#define GPIO_26_IOMUX_GPIOxx 1
-#define GPIO_74_IOMUX_ESPI_CLK2 0
-#define GPIO_74_IOMUX_GPIOxx 1
-#define GPIO_75_IOMUX_ESPI_CLK1 0
-#define GPIO_75_IOMUX_GPIOxx 1
-#define GPIO_76_IOMUX_GPIOxx 0
-#define GPIO_76_IOMUX_SPI_TPM_CS_L 1
-#define GPIO_86_IOMUX_NMI_SYNC_FLOOD_L 0
-#define GPIO_87_IOMUX_GPIOxx 0
-#define GPIO_88_IOMUX_GPIOxx 0
-#define GPIO_89_IOMUX_GENINT_L 0
-#define GPIO_89_IOMUX_PM_INTR_L 1
-#define GPIO_89_IOMUX_GPIOxx 2
-#define GPIO_104_IOMUX_GPIOxx 0
-#define GPIO_105_IOMUX_GPIOxx 0
-#define GPIO_106_IOMUX_GPIOxx 0
-#define GPIO_107_IOMUX_GPIOxx 0
-#define GPIO_108_IOMUX_ESPI0_ALERT_D1 0
-#define GPIO_108_IOMUX_GPIOxx 1
-#define GPIO_109_IOMUX_GPIOxx 0
-#define GPIO_110_IOMUX_ESPI1_ALERT_D1 0
-#define GPIO_110_IOMUX_GPIOxx 1
-#define GPIO_115_IOMUX_GPIOxx 0
-#define GPIO_115_IOMUX_CLK_REQ11_L 1
-#define GPIO_116_IOMUX_GPIOxx 0
-#define GPIO_116_IOMUX_CLK_REQ12_L 1
-#define GPIO_117_IOMUX_ESPI_CLK0 0
-#define GPIO_117_IOMUX_GPIOxx 1
-#define GPIO_118_IOMUX_SPI_CS0_L 0
-#define GPIO_118_IOMUX_GPIOxx 1
-#define GPIO_119_IOMUX_SPI_CS1_L 0
-#define GPIO_119_IOMUX_GPIOxx 1
-#define GPIO_120_IOMUX_ESPI0_DATA0 0
-#define GPIO_120_IOMUX_GPIOxx 1
-#define GPIO_121_IOMUX_ESPI0_DATA1 0
-#define GPIO_121_IOMUX_GPIOxx 1
-#define GPIO_122_IOMUX_ESPI0_DATA2 0
-#define GPIO_122_IOMUX_GPIOxx 1
-#define GPIO_123_IOMUX_ESPI0_DATA3 0
-#define GPIO_123_IOMUX_GPIOxx 1
-#define GPIO_124_IOMUX_ESPI_CS0_L 0
-#define GPIO_124_IOMUX_GPIOxx 1
-#define GPIO_125_IOMUX_ESPI_CS1_L 0
-#define GPIO_125_IOMUX_GPIOxx 1
-#define GPIO_126_IOMUX_SPI_CS2_L 0
-#define GPIO_126_IOMUX_GPIOxx 1
-#define GPIO_129_IOMUX_ESPI_RSTIN_L 0
-#define GPIO_129_IOMUX_KBRST_L 1
-#define GPIO_129_IOMUX_GPIOxx 2
-#define GPIO_131_IOMUX_ESPI1_DATA0 0
-#define GPIO_131_IOMUX_GPIOxx 1
-#define GPIO_132_IOMUX_ESPI1_DATA1 0
-#define GPIO_132_IOMUX_GPIOxx 1
-#define GPIO_133_IOMUX_ESPI1_DATA2 0
-#define GPIO_133_IOMUX_GPIOxx 1
-#define GPIO_134_IOMUX_ESPI1_DATA3 0
-#define GPIO_134_IOMUX_GPIOxx 1
-#define GPIO_135_IOMUX_UART0_CTS_L 0
-#define GPIO_135_IOMUX_UART2_TXD 1
-#define GPIO_135_IOMUX_GPIOxx 2
-#define GPIO_136_IOMUX_UART0_RXD 0
-#define GPIO_136_IOMUX_GPIOxx 1
-#define GPIO_137_IOMUX_UART0_RTS_L 0
-#define GPIO_137_IOMUX_UART2_RXD 1
-#define GPIO_137_IOMUX_GPIOxx 2
-#define GPIO_138_IOMUX_UART0_TXD 0
-#define GPIO_138_IOMUX_GPIOxx 1
-#define GPIO_139_IOMUX_UART0_INTR 0
-#define GPIO_139_IOMUX_GPIOxx 1
-#define GPIO_141_IOMUX_UART1_RXD 0
-#define GPIO_141_IOMUX_GPIOxx 1
-#define GPIO_142_IOMUX_UART1_TXD 0
-#define GPIO_142_IOMUX_GPIOxx 1
-#define GPIO_145_IOMUX_I3C0_SCL_SPD0_SCL 0
-#define GPIO_145_IOMUX_I2C0_SCL_SPD0_SCL 1
-#define GPIO_145_IOMUX_SMBUS0_SCL 2
-#define GPIO_145_IOMUX_GPIOxx 3
-#define GPIO_146_IOMUX_I3C0_SDA_SPD0_SDA 0
-#define GPIO_146_IOMUX_I2C0_SDA_SPD0_SDA 1
-#define GPIO_146_IOMUX_SMBUS0_SDA 2
-#define GPIO_146_IOMUX_GPIOxx 3
-#define GPIO_147_IOMUX_I3C1_SCL_SPD1_SCL 0
-#define GPIO_147_IOMUX_I2C1_SCL_SPD1_SCL 1
-#define GPIO_147_IOMUX_GPIOxx 2
-#define GPIO_148_IOMUX_I3C1_SDA_SPD1_SDA 0
-#define GPIO_148_IOMUX_I2C1_SDA_SPD1_SDA 1
-#define GPIO_148_IOMUX_GPIOxx 2
-#define GPIO_149_IOMUX_I3C2_SCL_SPD2_SCL 0
-#define GPIO_149_IOMUX_I2C2_SCL_SPD2_SCL 1
-#define GPIO_149_IOMUX_GPIOxx 2
-#define GPIO_150_IOMUX_I3C2_SDA_SPD2_SDA 0
-#define GPIO_150_IOMUX_I2C2_SDA_SPD2_SDA 1
-#define GPIO_150_IOMUX_GPIOxx 2
-#define GPIO_151_IOMUX_I3C3_SCL_SPD3_SCL 0
-#define GPIO_151_IOMUX_I2C3_SCL_SPD3_SCL 1
-#define GPIO_151_IOMUX_GPIOxx 2
-#define GPIO_152_IOMUX_I3C3_SDA_SPD3_SDA 0
-#define GPIO_152_IOMUX_I2C3_SDA_SPD3_SDA 1
-#define GPIO_152_IOMUX_GPIOxx 2
-
-/* Remote GPIOs */
-#define GPIO_256_IOMUX_GPIOxx 0
-#define GPIO_256_IOMUX_SGPIO0_CLK 1
-#define GPIO_257_IOMUX_GPIOxx 0
-#define GPIO_257_IOMUX_SGPIO1_CLK 1
-#define GPIO_257_IOMUX_CLK_REQ01_L 2
-#define GPIO_258_IOMUX_GPIOxx 0
-#define GPIO_258_IOMUX_SGPIO2_CLK 1
-#define GPIO_258_IOMUX_CLK_REQ02_L 2
-#define GPIO_259_IOMUX_GPIOxx 0
-#define GPIO_259_IOMUX_SGPIO3_CLK 1
-#define GPIO_260_IOMUX_SGPIO_DATAOUT 0
-#define GPIO_260_IOMUX_GPIOxx 1
-#define GPIO_261_IOMUX_SGPIO_LOAD 0
-#define GPIO_261_IOMUX_GPIOxx 1
-#define GPIO_262_IOMUX_GPIOxx 0
-#define GPIO_263_IOMUX_GPIOxx 0
-#define GPIO_264_IOMUX_USB00_OC_L 0
-#define GPIO_264_IOMUX_GPIOxx 1
-#define GPIO_265_IOMUX_USB01_OC_L 0
-#define GPIO_265_IOMUX_GPIOxx 1
-#define GPIO_266_IOMUX_PCIE_RST0_L 0
-#define GPIO_266_IOMUX_GPIOxx 1
-
-#endif /* AMD_GENOA_GPIO_H */
diff --git a/src/soc/amd/genoa/include/soc/i2c.h b/src/soc/amd/genoa/include/soc/i2c.h
deleted file mode 100644
index ffff754f1b..0000000000
--- a/src/soc/amd/genoa/include/soc/i2c.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_I2C_H
-#define AMD_GENOA_I2C_H
-
-#include <gpio.h>
-#include <types.h>
-
-#define GPIO_I2C0_SCL		BIT(0)
-#define GPIO_I2C1_SCL		BIT(1)
-#define GPIO_I2C2_SCL		BIT(2)
-#define GPIO_I2C3_SCL		BIT(3)
-#define GPIO_I2C4_SCL		BIT(4)
-#define GPIO_I2C5_SCL		BIT(5)
-#define GPIO_I2C_MASK		(GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
-				 GPIO_I2C2_SCL | GPIO_I2C3_SCL | \
-				 GPIO_I2C4_SCL | GPIO_I2C5_SCL)
-
-
-#define I2C0_SCL_PIN			GPIO_145
-#define I2C1_SCL_PIN			GPIO_147
-#define I2C2_SCL_PIN			GPIO_149
-#define I2C3_SCL_PIN			GPIO_151
-#define I2C4_SCL_PIN			GPIO_13
-#define I2C5_SCL_PIN			GPIO_19
-
-#define I2C0_SCL_PIN_IOMUX_GPIOxx	GPIO_145_IOMUX_GPIOxx
-#define I2C1_SCL_PIN_IOMUX_GPIOxx	GPIO_147_IOMUX_GPIOxx
-#define I2C2_SCL_PIN_IOMUX_GPIOxx	GPIO_149_IOMUX_GPIOxx
-#define I2C3_SCL_PIN_IOMUX_GPIOxx	GPIO_151_IOMUX_GPIOxx
-#define I2C4_SCL_PIN_IOMUX_GPIOxx	GPIO_13_IOMUX_GPIOxx
-#define I2C5_SCL_PIN_IOMUX_GPIOxx	GPIO_19_IOMUX_GPIOxx
-
-void reset_i2c_peripherals(void);
-
-#endif /* AMD_GENOA_I2C_H */
diff --git a/src/soc/amd/genoa/include/soc/iomap.h b/src/soc/amd/genoa/include/soc/iomap.h
deleted file mode 100644
index 0e24780a0f..0000000000
--- a/src/soc/amd/genoa/include/soc/iomap.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_IOMAP_H
-#define AMD_GENOA_IOMAP_H
-
-#define I2C_MASTER_DEV_COUNT		6
-#define I2C_PERIPHERAL_DEV_COUNT	0
-#define I2C_CTRLR_COUNT			(I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
-
-#define SPI_BASE_ADDRESS		0xfec10000
-
-/* @Todo : Check these values for Genoa */
-
-/* I/O Ranges */
-#define ACPI_IO_BASE			0x0400
-#define  ACPI_CSTATE_CONTROL		(ACPI_IO_BASE + 0x10)
-
-/* FCH AL2AHB Registers */
-#define ALINK_AHB_ADDRESS		0xfedc0000
-
-#define APU_I2C0_BASE			0xfedc2000
-#define APU_I2C1_BASE			0xfedc3000
-#define APU_I2C2_BASE			0xfedc4000
-#define APU_I2C3_BASE			0xfedc5000
-#define APU_I2C4_BASE			0xfedc6000
-#define APU_I2C5_BASE			0xfedcb000
-
-#define APU_UART0_BASE			0xfedc9000
-#define APU_UART1_BASE			0xfedca000
-#define APU_UART2_BASE			0xfedce000
-
-#define APU_I3C0_BASE			0xfedd2000
-#define APU_I3C1_BASE			0xfedd3000
-#define APU_I3C2_BASE			0xfedd4000
-#define APU_I3C3_BASE			0xfedd6000
-
-#endif /* AMD_GENOA_IOMAP_H */
diff --git a/src/soc/amd/genoa/include/soc/lpc.h b/src/soc/amd/genoa/include/soc/lpc.h
deleted file mode 100644
index f98ffe8ef8..0000000000
--- a/src/soc/amd/genoa/include/soc/lpc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_LPC_H
-#define AMD_GENOA_LPC_H
-
-#define SPI_BASE_ADDRESS_REGISTER	0xa0
-#define   SPI_BASE_ALIGNMENT		BIT(8)
-#define   SPI_BASE_RESERVED		(BIT(5) | BIT(6) | BIT(7))
-#define   PSP_SPI_MMIO_SEL		BIT(4)
-#define   ROUTE_TPM_2_SPI		BIT(3)
-#define   SPI_ABORT_ENABLE		BIT(2)
-#define   SPI_ROM_ENABLE		BIT(1)
-#define   SPI_ROM_ALT_ENABLE		BIT(0)
-#define   SPI_PRESERVE_BITS		(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
-
-#endif /* AMD_GENOA_LPC_H */
diff --git a/src/soc/amd/genoa/include/soc/msr.h b/src/soc/amd/genoa/include/soc/msr.h
deleted file mode 100644
index 368c631d7d..0000000000
--- a/src/soc/amd/genoa/include/soc/msr.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_MSR_H
-#define AMD_GENOA_MSR_H
-
-/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
-union pstate_msr {
-	struct {
-		uint64_t cpu_fid_0_7	:  8; /* [ 0.. 7] */
-		uint64_t cpu_dfs_id	:  6; /* [ 8..13] */
-		uint64_t cpu_vid_0_7	:  8; /* [14..21] */
-		uint64_t idd_value	:  8; /* [22..29] */
-		uint64_t idd_div	:  2; /* [30..31] */
-		uint64_t cpu_vid_8	:  1; /* [32..32] */
-		uint64_t		: 30; /* [33..62] */
-		uint64_t pstate_en	:  1; /* [63..63] */
-	};
-	uint64_t raw;
-};
-
-
-/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
-#define MSR_CPPC_CAPABILITY_1				0xc00102b0
-#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF		24
-#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF		16
-#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF	8
-#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF		0
-
-#define MSR_CPPC_ENABLE				0xc00102b1
-#define MSR_CPPC_REQUEST			0xc00102b3
-#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF	24
-#define SHIFT_CPPC_REQUEST_DES_PERF		16
-#define SHIFT_CPPC_REQUEST_MIN_PERF		8
-#define SHIFT_CPPC_REQUEST_MAX_PERF		0
-
-#define MSR_CPPC_STATUS		0xc00102b4
-
-#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
-#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8
-
-#endif /* AMD_GENOA_MSR_H */
diff --git a/src/soc/amd/genoa/include/soc/nvs.h b/src/soc/amd/genoa/include/soc/nvs.h
deleted file mode 100644
index cbc9ba9b4d..0000000000
--- a/src/soc/amd/genoa/include/soc/nvs.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/* TODO: Check if this is still correct */
-
-/*
- * NOTE: The layout of the global_nvs structure below must match the layout
- * in soc/soc/amd/genoa/acpi/globalnvs.asl !!!
- *
- */
-
-#ifndef AMD_GENOA_NVS_H
-#define AMD_GENOA_NVS_H
-
-#include <stdint.h>
-
-struct __packed global_nvs {
-	/* Miscellaneous */
-	uint64_t	pm1i; /* 0x00 - 0x07 - System Wake Source - PM1 Index */
-	uint64_t	gpei; /* 0x08 - 0x0f - GPE Wake Source */
-};
-
-#endif /* AMD_GENOA_NVS_H */
diff --git a/src/soc/amd/genoa/include/soc/pci_devs.h b/src/soc/amd/genoa/include/soc/pci_devs.h
deleted file mode 100644
index d314deb4a5..0000000000
--- a/src/soc/amd/genoa/include/soc/pci_devs.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_PCI_DEVS_H
-#define AMD_GENOA_PCI_DEVS_H
-
-#include <device/pci_def.h>
-#include <amdblocks/pci_devs.h>
-
-/* GNB Root Complex */
-#define GNB_DEV			0x0
-#define GNB_FUNC		0
-#define GNB_DEVFN		PCI_DEVFN(GNB_DEV, GNB_FUNC)
-#define SOC_GNB_DEV		_SOC_DEV(GNB_DEV, GNB_FUNC)
-
-/* SMBUS */
-#define SMBUS_DEV		0x14
-#define SMBUS_FUNC		0
-#define SMBUS_DEVFN		PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
-#define SOC_SMBUS_DEV		_SOC_DEV(SMBUS_DEV, SMBUS_FUNC)
-
-/* Data Fabric functions */
-#define DF_DEV			0x18
-
-#define DF_F0_DEVFN		PCI_DEVFN(DF_DEV, 0)
-#define SOC_DF_F0_DEV		_SOC_DEV(DF_DEV, 0)
-
-#define DF_F1_DEVFN		PCI_DEVFN(DF_DEV, 1)
-#define SOC_DF_F1_DEV		_SOC_DEV(DF_DEV, 1)
-
-#define DF_F2_DEVFN		PCI_DEVFN(DF_DEV, 2)
-#define SOC_DF_F2_DEV		_SOC_DEV(DF_DEV, 2)
-
-#define DF_F3_DEVFN		PCI_DEVFN(DF_DEV, 3)
-#define SOC_DF_F3_DEV		_SOC_DEV(DF_DEV, 3)
-
-#define DF_F4_DEVFN		PCI_DEVFN(DF_DEV, 4)
-#define SOC_DF_F4_DEV		_SOC_DEV(DF_DEV, 4)
-
-#define DF_F5_DEVFN		PCI_DEVFN(DF_DEV, 5)
-#define SOC_DF_F5_DEV		_SOC_DEV(DF_DEV, 5)
-
-#define DF_F6_DEVFN		PCI_DEVFN(DF_DEV, 6)
-#define SOC_DF_F6_DEV		_SOC_DEV(DF_DEV, 6)
-
-#define DF_F7_DEVFN		PCI_DEVFN(DF_DEV, 7)
-#define SOC_DF_F7_DEV		_SOC_DEV(DF_DEV, 7)
-
-#endif
diff --git a/src/soc/amd/genoa/include/soc/smi.h b/src/soc/amd/genoa/include/soc/smi.h
deleted file mode 100644
index c9054c53c1..0000000000
--- a/src/soc/amd/genoa/include/soc/smi.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef AMD_GENOA_SMI_H
-#define AMD_GENOA_SMI_H
-
-#include <types.h>
-
-#define SMI_GEVENTS			24
-#define SCIMAPS				64 /* 0..63 */
-#define SCI_GPES			32
-#define NUMBER_SMITYPES			157
-
-#define SMI_EVENT_STATUS		0x0
-#define SMI_EVENT_ENABLE		0x04
-#define SMI_SCI_TRIG			0x08
-#define SMI_SCI_LEVEL			0x0c
-#define SMI_SCI_STATUS			0x10
-#define SMI_SCI_EN			0x14
-#define SMI_SCI_MAP0			0x40
-# define SMI_SCI_MAP(X)			(SMI_SCI_MAP0 + (X))
-
-/* SMI source and status */
-#define SMITYPE_G_GENINT1_L		0
-#define SMITYPE_G_AGPIO115		1
-#define SMITYPE_G_AGPIO3		2
-#define SMITYPE_G_AGPIO22		3
-#define SMITYPE_G_AGPIO4		4
-#define SMITYPE_G_AGPIO21		5
-#define SMITYPE_G_AGPIO116		6
-#define SMITYPE_G_AGPIO5		7
-#define SMITYPE_G_WAKE_L		8
-#define SMITYPE_G_NMI_SYNC_FLOOD	9
-#define SMITYPE_G_AGPIO6		10
-#define SMITYPE_G_AGPIO76		11
-#define SMITYPE_G_USBOC0_L		12
-#define SMITYPE_G_USBOC1_L		13
-#define SMITYPE_G_SMERR_L		14
-#define SMITYPE_G_PCIE_RST1_L		15
-#define SMITYPE_G_ESPI_RSTOUT_L		16
-#define SMITYPE_G_ESPI_RSTIN_L		17
-#define SMITYPE_G_X48M_OUT		18
-#define SMITYPE_G_SYSRESET_L		19
-#define SMITYPE_G_AGPIO104		20
-#define SMITYPE_G_PWR_BTN_L		21
-#define SMITYPE_G_AGPI105		22
-#define SMITYPE_G_AGPI106		23
-#define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L)		\
-		   | (1 << SMITYPE_G_AGPIO115)		\
-		   | (1 << SMITYPE_G_AGPIO3)		\
-		   | (1 << SMITYPE_G_AGPIO22)		\
-		   | (1 << SMITYPE_G_AGPIO4)		\
-		   | (1 << SMITYPE_G_AGPIO21)		\
-		   | (1 << SMITYPE_G_AGPIO116)		\
-		   | (1 << SMITYPE_G_AGPIO5)		\
-		   | (1 << SMITYPE_G_WAKE_L)		\
-		   | (1 << SMITYPE_G_NMI_SYNC_FLOOD)	\
-		   | (1 << SMITYPE_G_AGPIO6)		\
-		   | (1 << SMITYPE_G_AGPIO76)		\
-		   | (1 << SMITYPE_G_USBOC0_L)		\
-		   | (1 << SMITYPE_G_USBOC1_L)		\
-		   | (1 << SMITYPE_G_SMERR_L)		\
-		   | (1 << SMITYPE_G_PCIE_RST1_L)	\
-		   | (1 << SMITYPE_G_ESPI_RSTOUT_L)	\
-		   | (1 << SMITYPE_G_ESPI_RSTIN_L)	\
-		   | (1 << SMITYPE_G_X48M_OUT)		\
-		   | (1 << SMITYPE_G_SYSRESET_L)	\
-		   | (1 << SMITYPE_G_AGPIO104)		\
-		   | (1 << SMITYPE_G_PWR_BTN_L)		\
-		   | (1 << SMITYPE_G_AGPI105)		\
-		   | (1 << SMITYPE_G_AGPI106))
-#define SMITYPE_MP2_WAKE		24
-#define SMITYPE_MP2_GPIO0		25
-#define SMITYPE_ESPI_SYS		26
-#define SMITYPE_ESPI_WAKE_PME		27
-#define SMITYPE_MP2_GPIO1		28
-#define SMITYPE_GPP_PME			29
-#define SMITYPE_NB_GPP_HOT_PLUG		30
-/* 31 Reserved */
-#define SMITYPE_WAKE_L2			32
-#define SMITYPE_PSP			33
-/* 34-35 Reserved */
-#define SMITYPE_ESPI_SCI_B		36
-#define SMITYPE_ESPI1_SYS_EVT_B		37
-#define SMITYPE_ESPI1_WAKE_PME		38
-#define SMITYPE_AZPME			39
-#define SMITYPE_USB_PD_I2C4		40
-#define SMITYPE_GPIO_CTL		41
-#define SMITYPE_ESPI1_SCI_B		42
-#define SMITYPE_ALT_HPET_ALARM		43
-#define SMITYPE_FAN_THERMAL		44
-#define SMITYPE_ASF_MASTER_SLAVE	45
-#define SMITYPE_I2S_WAKE		46
-#define SMITYPE_SMBUS0_MASTER		47
-#define SMITYPE_TWARN			48
-#define SMITYPE_TRAFFIC_MON		49
-#define SMITYPE_ILLB			50
-#define SMITYPE_PWRBUTTON_UP		51
-#define SMITYPE_PROCHOT			52
-#define SMITYPE_APU_HW			53
-#define SMITYPE_NB_SCI			54
-#define SMITYPE_RAS_SERR		55
-#define SMITYPE_XHC0_PME		56
-#define SMITYPE_XHC1_PME		57
-#define SMITYPE_ACDC_TIMER		58
-/* 59-63 Reserved */
-#define SMITYPE_KB_RESET		64
-#define SMITYPE_SLP_TYP			65
-#define SMITYPE_AL2H_ACPI		66
-/* 67-71 Reserved */
-#define SMITYPE_GBL_RLS			72
-#define SMITYPE_BIOS_RLS		73
-#define SMITYPE_PWRBUTTON_DOWN		74
-#define SMITYPE_SMI_CMD_PORT		75
-#define SMITYPE_USB_SMI			76
-#define SMITYPE_SERIRQ			77
-#define SMITYPE_SMBUS0_INTR		78
-/* 79-80 Reserved */
-#define SMITYPE_INTRUDER		81
-#define SMITYPE_VBAT_LOW		82
-#define SMITYPE_PROTHOT			83
-#define SMITYPE_PCI_SERR		84
-/* 85-89 Reserved */
-#define SMITYPE_EMUL60_64		90
-/* 91-132 Reserved */
-#define SMITYPE_FANIN0			133
-/* 134-140 Reserved */
-#define SMITYPE_CF9_WRITE		141
-#define SMITYPE_SHORT_TIMER		142
-#define SMITYPE_LONG_TIMER		143
-#define SMITYPE_AB_SMI			144
-/* 145 Reserved */
-#define SMITYPE_ESPI_SMI		146
-#define SMITYPE_ESPI1_SMI		147
-#define SMITYPE_IOTRAP0			148
-#define SMITYPE_IOTRAP1			149
-#define SMITYPE_IOTRAP2			150
-#define SMITYPE_IOTRAP3			151
-#define SMITYPE_MEMTRAP0		152
-/* 153-155 Reserved */
-#define SMITYPE_CFGTRAP0		156
-/* 157-159 Reserved */
-
-#define TYPE_TO_MASK(X)				(1 << (X) % 32)
-
-#define SMI_REG_SMISTS0			0x80
-#define SMI_REG_SMISTS1			0x84
-#define SMI_REG_SMISTS2			0x88
-#define SMI_REG_SMISTS3			0x8c
-#define SMI_REG_SMISTS4			0x90
-
-#define SMI_REG_POINTER			0x94
-# define SMI_STATUS_SRC_SCI			(1 << 0)
-# define SMI_STATUS_SRC_0			(1 << 1) /* SMIx80 */
-# define SMI_STATUS_SRC_1			(1 << 2) /* SMIx84... */
-# define SMI_STATUS_SRC_2			(1 << 3)
-# define SMI_STATUS_SRC_3			(1 << 4)
-# define SMI_STATUS_SRC_4			(1 << 5)
-
-#define SMI_TIMER			0x96
-#define SMI_TIMER_MASK				0x7fff
-#define SMI_TIMER_EN				(1 << 15)
-
-#define SMI_REG_SMITRIG0		0x98
-# define SMITRIG0_PSP				(1 << 25)
-# define SMITRG0_EOS				(1 << 28)
-# define SMI_TIMER_SEL				(1 << 29)
-# define SMITRG0_SMIENB				(1 << 31)
-
-#define SMI_REG_CONTROL0		0xa0
-#define SMI_REG_CONTROL1		0xa4
-#define SMI_REG_CONTROL2		0xa8
-#define SMI_REG_CONTROL3		0xac
-#define SMI_REG_CONTROL4		0xb0
-#define SMI_REG_CONTROL5		0xb4
-#define SMI_REG_CONTROL6		0xb8
-#define SMI_REG_CONTROL7		0xbc
-#define SMI_REG_CONTROL8		0xc0
-#define SMI_REG_CONTROL9		0xc4
-
-#define SMI_MODE_MASK			0x03
-
-#endif /* AMD_GENOA_SMI_H */
diff --git a/src/soc/amd/genoa/include/soc/smu.h b/src/soc/amd/genoa/include/soc/smu.h
deleted file mode 100644
index 6ab0c063e5..0000000000
--- a/src/soc/amd/genoa/include/soc/smu.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_SMU_H
-#define AMD_GENOA_SMU_H
-
-/* SMU mailbox register offsets in SMN */
-#define SMN_SMU_MESG_ID		0x3b10530
-#define SMN_SMU_MESG_RESP	0x3b1057c
-#define SMN_SMU_MESG_ARGS_BASE	0x3b109c4
-
-#define SMU_NUM_ARGS		6
-
-enum smu_message_id {
-	SMC_MSG_S3ENTRY = 0x0b,
-};
-
-/*
- * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines S-State and
- * SlpTypeEn gets set by the SMU. Function does not return if successful.
- */
-void smu_sx_entry(void);
-
-#endif /* AMD_GENOA_SMU_H */
diff --git a/src/soc/amd/genoa/include/soc/soc_chip.h b/src/soc/amd/genoa/include/soc/soc_chip.h
deleted file mode 100644
index d5dae9add8..0000000000
--- a/src/soc/amd/genoa/include/soc/soc_chip.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_GENOA_SOC_CHIP_H_
-#define _SOC_GENOA_SOC_CHIP_H_
-
-#include "../../chip.h"
-
-#endif
diff --git a/src/soc/amd/genoa/include/soc/southbridge.h b/src/soc/amd/genoa/include/soc/southbridge.h
deleted file mode 100644
index 148ebfcbf4..0000000000
--- a/src/soc/amd/genoa/include/soc/southbridge.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_SOUTHBRIDGE_H
-#define AMD_GENOA_SOUTHBRIDGE_H
-
-#include <soc/iomap.h>
-
-/* Power management registers:  0xfed80300 or index/data at IO 0xcd6/cd7 */
-#define PM_ISACONTROL			0x04
-#define   ABCLKGATEEN			BIT(16)
-#define PM_PCI_CTRL			0x08
-#define   FORCE_SLPSTATE_RETRY		BIT(25)
-#define PWR_RESET_CFG			0x10
-#define   TOGGLE_ALL_PWR_GOOD		(1 << 1)
-#define PM_SERIRQ_CONF			0x54
-#define   PM_SERIRQ_NUM_BITS_17		0x0000
-#define   PM_SERIRQ_NUM_BITS_18		0x0004
-#define   PM_SERIRQ_NUM_BITS_19		0x0008
-#define   PM_SERIRQ_NUM_BITS_20		0x000c
-#define   PM_SERIRQ_NUM_BITS_21		0x0010
-#define   PM_SERIRQ_NUM_BITS_22		0x0014
-#define   PM_SERIRQ_NUM_BITS_23		0x0018
-#define   PM_SERIRQ_NUM_BITS_24		0x001c
-#define   PM_SERIRQ_MODE		BIT(6)
-#define   PM_SERIRQ_ENABLE		BIT(7)
-#define PM_EVT_BLK			0x60
-#define   WAK_STS			BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
-#define   PCIEXPWAK_STS			BIT(14)
-#define   RTC_STS			BIT(10)
-#define   PWRBTN_STS			BIT(8)
-#define   GBL_STS			BIT(5)
-#define   BM_STS			BIT(4)
-#define   TIMER_STS			BIT(0)
-#define   PCIEXPWAK_DIS			BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */
-#define   RTC_EN			BIT(10)
-#define   PWRBTN_EN			BIT(8)
-#define   GBL_EN			BIT(5)
-#define   TIMER_STS			BIT(0)
-#define PM1_CNT_BLK			0x62
-#define PM_TMR_BLK			0x64
-#define PM_GPE0_BLK			0x68
-#define PM_ACPI_SMI_CMD			0x6a
-#define PM_ACPI_CONF			0x74
-#define   PM_ACPI_DECODE_STD		BIT(0)
-#define   PM_ACPI_GLOBAL_EN		BIT(1)
-#define   PM_ACPI_RTC_EN_EN		BIT(2)
-#define   PM_ACPI_SLPBTN_EN_EN		BIT(3)
-#define   PM_ACPI_TIMER_EN_EN		BIT(4)
-#define   PM_ACPI_MASK_ARB_DIS		BIT(6)
-#define   PM_ACPI_BIOS_RLS		BIT(7)
-#define   PM_ACPI_PWRBTNEN_EN		BIT(8)
-#define   PM_ACPI_REDUCED_HW_EN		BIT(9)
-#define   PM_ACPI_S5_LPC_PIN_MODE_SEL	BIT(10)
-#define   PM_ACPI_S5_LPC_PIN_MODE	BIT(11)
-#define   PM_ACPI_LPC_RST_DIS		BIT(12)
-#define   PM_ACPI_SEL_PWRGD_PAD		BIT(13)
-#define   PM_ACPI_SEL_SMU_THERMTRIP	BIT(14)
-#define   PM_ACPI_SW_S5PWRMUX_OVRD_N	BIT(15)
-#define   PM_ACPI_SW_S5PWRMUX		BIT(16)
-#define   PM_ACPI_EN_SHUTDOWN_MSG	BIT(17)
-#define   PM_ACPI_EN_SYNC_FLOOD		BIT(18)
-#define   PM_ACPI_FORCE_SPIUSEPIN_0	BIT(19)
-#define   PM_ACPI_EN_DF_INTRWAKE	BIT(20)
-#define   PM_ACPI_MASK_USB_S5_RST	BIT(21)
-#define   PM_ACPI_USE_RSMU_RESET	BIT(22)
-#define   PM_ACPI_RST_USB_S5		BIT(23)
-#define   PM_ACPI_BLOCK_PCIE_PME	BIT(24)
-#define   PM_ACPI_PCIE_WAK_MASK		BIT(25)
-#define   PM_ACPI_PCIE_WAK_INTR_DIS	BIT(26)
-#define   PM_ACPI_WAKE_AS_GEVENT	BIT(27)
-#define   PM_ACPI_NB_PME_GEVENT		BIT(28)
-#define   PM_ACPI_RTC_WAKE_EN		BIT(29)
-#define   PM_ACPI_USE_GATED_ALINK_CLK	BIT(30)
-#define   PM_ACPI_DELAY_GPP_OFF_TIME	BIT(31)
-#define PM_SPI_PAD_PU_PD		0x90
-#define   PM_ESPI_CS_USE_DATA2		BIT(16)
-#define PM_LPC_GATING			0xec
-#define   PM_LPC_AB_NO_BYPASS_EN	BIT(2)
-#define   PM_LPC_A20_EN			BIT(1)
-#define   PM_LPC_ENABLE			BIT(0)
-
-#define PM1_LIMIT			16
-#define GPE0_LIMIT			32
-#define TOTAL_BITS(a)			(8 * sizeof(a))
-
-#define FCH_LEGACY_UART_DECODE		(ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
-
-/* FCH MISC Registers 0xfed80e00 */
-#define GPP_CLK_CNTRL			0x00
-#define   GPP_CLK0_REQ_SHIFT		0
-#define   GPP_CLK1_REQ_SHIFT		2
-#define   GPP_CLK4_REQ_SHIFT		4
-#define   GPP_CLK2_REQ_SHIFT		6
-#define   GPP_CLK3_REQ_SHIFT		8
-#define   GPP_CLK5_REQ_SHIFT		10
-#define   GPP_CLK6_REQ_SHIFT		12
-#define     GPP_CLK_OUTPUT_COUNT	7
-#define     GPP_CLK_OUTPUT_AVAILABLE	4
-#define   GPP_CLK_REQ_MASK(clk_shift)	(0x3 << (clk_shift))
-#define   GPP_CLK_REQ_ON(clk_shift)	(0x3 << (clk_shift))
-#define   GPP_CLK_REQ_EXT(clk_shift)	(0x1 << (clk_shift))
-#define   GPP_CLK_REQ_OFF(clk_shift)	(0x0 << (clk_shift))
-
-#define MISC_CLKGATEDCNTL		0x2c
-#define   ALINKCLK_GATEOFFEN		BIT(16)
-#define   BLINKCLK_GATEOFFEN		BIT(17)
-#define   XTAL_PAD_S0I3_TURNOFF_EN	BIT(19)
-#define   XTAL_PAD_S3_TURNOFF_EN	BIT(20)
-#define   XTAL_PAD_S5_TURNOFF_EN	BIT(21)
-#define MISC_CGPLL_CONFIGURATION0	0x30
-#define   USB_PHY_CMCLK_S3_DIS		BIT(8)
-#define   USB_PHY_CMCLK_S0I3_DIS	BIT(9)
-#define   USB_PHY_CMCLK_S5_DIS		BIT(10)
-#define MISC_CLK_CNTL0			0x40 /* named MISC_CLK_CNTL1 on Picasso */
-#define   BP_X48M0_S0I3_DIS		BIT(4)
-#define   BP_X48M0_OUTPUT_EN		BIT(2) /* 1=En, unlike Hudson, Kern */
-
-void fch_pre_init(void);
-void fch_early_init(void);
-
-#endif /* AMD_GENOA_SOUTHBRIDGE_H */
diff --git a/src/soc/amd/genoa/include/soc/uart.h b/src/soc/amd/genoa/include/soc/uart.h
deleted file mode 100644
index ae8f118461..0000000000
--- a/src/soc/amd/genoa/include/soc/uart.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_GENOA_UART_H
-#define AMD_GENOA_UART_H
-
-#include <types.h>
-
-void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */
-
-#endif /* AMD_GENOA_UART_H */