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authorArthur Heymans <arthur@aheymans.xyz>2023-07-13 12:34:04 +0200
committerMartin L Roth <gaumless@gmail.com>2023-09-01 21:07:10 +0000
commit6d3682ee9b19b9e6833f38046891132be665c93c (patch)
tree5b74f124c101a1b36bd4448956e0358becf61784 /src/soc/amd/genoa/include
parent372c4151d4423788e597c1fdf90e003ce4226649 (diff)
soc/amd/genoa: Add minimal viable code for compilation
This adds a dummy soc (genoa) based on EXAMPLE_MIN86 with amd linker script hooked up. Default to 64bit code as that will be a sensible default for this platform (high memory access required for RAS setup). Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I69253466084d17c4359d7e824d69f12490b076e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76495 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/genoa/include')
-rw-r--r--src/soc/amd/genoa/include/soc/iomap.h26
-rw-r--r--src/soc/amd/genoa/include/soc/southbridge.h12
2 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/include/soc/iomap.h b/src/soc/amd/genoa/include/soc/iomap.h
new file mode 100644
index 0000000000..076938e302
--- /dev/null
+++ b/src/soc/amd/genoa/include/soc/iomap.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_GENOA_IOMAP_H
+#define AMD_GENOA_IOMAP_H
+
+#define SPI_BASE_ADDRESS 0xfec10000
+
+/* @Todo : Check these values for Genoa */
+
+/* I/O Ranges */
+#define ACPI_IO_BASE 0x0400
+#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10)
+
+/* FCH AL2AHB Registers */
+#define ALINK_AHB_ADDRESS 0xfedc0000
+
+#define APU_I2C0_BASE 0xfedc2000
+#define APU_I2C1_BASE 0xfedc3000
+#define APU_I2C2_BASE 0xfedc4000
+#define APU_I2C3_BASE 0xfedc5000
+
+#define APU_UART0_BASE 0xfedc9000
+#define APU_UART1_BASE 0xfedca000
+#define APU_UART2_BASE 0xfedce000
+
+#endif /* AMD_GENOA_IOMAP_H */
diff --git a/src/soc/amd/genoa/include/soc/southbridge.h b/src/soc/amd/genoa/include/soc/southbridge.h
new file mode 100644
index 0000000000..95c054c531
--- /dev/null
+++ b/src/soc/amd/genoa/include/soc/southbridge.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_GENOA_SOUTHBRIDGE_H
+#define AMD_GENOA_SOUTHBRIDGE_H
+
+#include <soc/iomap.h>
+
+
+void fch_pre_init(void);
+void fch_early_init(void);
+
+#endif /* AMD_GENOA_SOUTHBRIDGE_H */