soc/amd/genoa: rename to genoa_poc

Even though this SoC is called 'Genoa', the openSIL implementation and
the corresponding coreboot integration is only a proof of concept that
isn't fully featured, has known limitations and bugs, and is not meant
for or ready to being productized. Adding the proof of concept suffix to
the name should point this out clearly enough so that no potential
customer could infer that this might be a fully functional and supported
implementation which it is not.

Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 72 deletions

diff --git a/src/soc/amd/genoa/chip.h b/src/soc/amd/genoa/chip.h
deleted file mode 100644
index 5577c12d85..0000000000
--- a/src/soc/amd/genoa/chip.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __GENOA_CHIP_H__
-#define __GENOA_CHIP_H__
-
-#include <amdblocks/chip.h>
-#include <amdblocks/i2c.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/iomap.h>
-#include <types.h>
-
-struct usb31_phy_settings {
-	uint8_t rx_ana_iq_phase_adjust;
-	uint8_t rx_eq_delta_iq_ovrd_en;
-	uint8_t rx_eq_delta_iq_ovrd_val;
-	uint8_t rx_iq_phase_adjust;
-	uint8_t tx_vboost_lvl_en;
-	uint8_t tx_vboost_lvl;
-	uint8_t rx_vref_ctrl_en;
-	uint8_t rx_vref_ctrl;
-	uint8_t tx_vboost_lvl_en_x;
-	uint8_t tx_vboost_lvl_x;
-	uint8_t rx_vref_ctrl_en_x;
-	uint8_t rx_vref_ctrl_x;
-};
-
-struct soc_usb_config {
-	uint8_t xhci0_enable : 1;
-	uint8_t xhci1_enable : 1;
-	struct {
-		uint8_t port0 : 4;
-		uint8_t port1 : 4;
-		uint8_t port2 : 4;
-		uint8_t port3 : 4;
-		uint8_t port4 : 4;
-		uint8_t port5 : 4;
-		uint8_t port6 : 4;
-		uint8_t port7 : 4;
-	} usb2_oc_pins[2];
-	struct {
-		uint8_t port0 : 4;
-		uint8_t port1 : 4;
-		uint8_t port2 : 4;
-		uint8_t port3 : 4;
-	}  usb3_oc_pins[2];
-	bool polarity_cfg_low;
-	union {
-		struct {
-			uint8_t port0 : 2;
-			uint8_t port1 : 2;
-			uint8_t port2 : 2; /* Broken in OpenSIL */
-			uint8_t port3 : 2; /* Broken in OpenSIL */
-		};
-		uint8_t raw;
-	} usb3_force_gen1;
-	bool usb31_phy_enable;
-	struct usb31_phy_settings usb31_phy[8];
-	bool s1_usb31_phy_enable;
-	struct usb31_phy_settings s1_usb31_phy[8];
-
-};
-
-struct soc_amd_genoa_config {
-	struct soc_amd_common_config common_config;
-
-	u8 i2c_scl_reset;
-	struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
-
-	struct soc_usb_config usb;
-};
-
-#endif