soc/amd/genoa: Add minimal viable code for compilation

This adds a dummy soc (genoa) based on EXAMPLE_MIN86 with
amd linker script hooked up.

Default to 64bit code as that will be a sensible default for this
platform (high memory access required for RAS setup).

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I69253466084d17c4359d7e824d69f12490b076e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76495
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

1 files changed, 13 insertions, 0 deletions

diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc
new file mode 100644
index 0000000000..01b1965b04
--- /dev/null
+++ b/src/soc/amd/genoa/Makefile.inc
@@ -0,0 +1,13 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ifeq ($(CONFIG_SOC_AMD_GENOA),y)
+
+bootblock-y	+= early_fch.c
+
+romstage-y	+= romstage.c
+
+ramstage-y	+= chip.c
+ramstage-y	+= timer.c
+
+CPPFLAGS_common += -I$(src)/soc/amd/genoa/include
+
+endif