diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-07-13 12:52:49 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-28 16:28:03 +0000 |
| commit | 8f1c70706056723f2be33ef15b1bc06092f1160f (patch) | |
| tree | 741ad31925a2b22424a87658ca5cd0c0a3605843 /src/soc/amd/genoa/Kconfig | |
| parent | 6f4a9497ae97dcbc3b7cc98a2ce990ecdb797f4e (diff) | |
soc/amd/genoa: Add Kconfig/Makefile to generate PSP image
TESTED: AMD onyx reaches x86 code
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: I95d84f93663a80f322fd4d7cdeb35ccfe0ec7d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76498
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/genoa/Kconfig')
| -rw-r--r-- | src/soc/amd/genoa/Kconfig | 60 |
1 files changed, 59 insertions, 1 deletions
diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 0331e36518..705805edc8 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -74,4 +74,62 @@ config ROMSTAGE_SIZE help Sets the size of DRAM allocation for romstage in linker script. -endif +menu "PSP Configuration Options" + +config AMDFW_CONFIG_FILE + string + default "src/soc/amd/genoa/fw.cfg" + +config PSP_DISABLE_POSTCODES + bool "Disable PSP post codes" + help + Disables the output of port80 post codes from PSP. + +config PSP_INIT_ESPI + bool "Initialize eSPI in PSP Stage 2 Boot Loader" + help + Select to initialize the eSPI controller in the PSP Stage 2 Boot + Loader. + +config PSP_UNLOCK_SECURE_DEBUG + bool + default y + +config HAVE_PSP_WHITELIST_FILE + bool "Include a debug whitelist file in PSP build" + default n + help + Support secured unlock prior to reset using a whitelisted + serial number. This feature requires a signed whitelist image + and bootloader from AMD. + + If unsure, answer 'n' + +config PSP_WHITELIST_FILE + string "Debug whitelist file path" + depends on HAVE_PSP_WHITELIST_FILE + +config HAVE_SPL_FILE + bool + +config SPL_TABLE_FILE + string "SPL table file" + depends on HAVE_SPL_FILE + default "3rdparty/amd_blobs_internal/genoa/PSP/Typex55_0_0_0_BLAntiRB.bin" + +config PSP_SOFTFUSE_BITS + string "PSP Soft Fuse bits to enable" + default "" + help + Space separated list of Soft Fuse bits to enable. + Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) + Bit 7: Disable PSP postcodes on Renoir and newer chips only + (Set by PSP_DISABLE_PORT80) + Bit 15: PSP debug output destination: + 0=SoC MMIO UART, 1=IO port 0x3F8 + + See #57299 (NDA) for additional bit definitions. +endmenu + + +endif # SOC_AMD_GENOA |