soc/amd/common/acp: introduce acp_gen1

Refactor existing acp code into acp_gen1 variant as preparation for gen2
variant in sabrina.

Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

5 files changed, 57 insertions, 38 deletions

diff --git a/src/soc/amd/common/block/acp/Kconfig b/src/soc/amd/common/block/acp/Kconfig
index ca733cd5de..7747c9359e 100644
--- a/src/soc/amd/common/block/acp/Kconfig
+++ b/src/soc/amd/common/block/acp/Kconfig
@@ -1,4 +1,5 @@
-config SOC_AMD_COMMON_BLOCK_ACP
+config SOC_AMD_COMMON_BLOCK_ACP_GEN1
 	bool
 	help
 	  Select this option to perform Audio Co-Processor(ACP) configuration.
+	  Used by the ACP in AMD family 17h, 19h, and earlier (picasso, cezanne)
diff --git a/src/soc/amd/common/block/acp/Makefile.inc b/src/soc/amd/common/block/acp/Makefile.inc
index cdff5bdb76..311fb75662 100644
--- a/src/soc/amd/common/block/acp/Makefile.inc
+++ b/src/soc/amd/common/block/acp/Makefile.inc
@@ -1 +1,2 @@
-ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP) += acp.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp_gen1.c
diff --git a/src/soc/amd/common/block/acp/acp.c b/src/soc/amd/common/block/acp/acp.c
index 465a44e2b6..057d50ad96 100644
--- a/src/soc/amd/common/block/acp/acp.c
+++ b/src/soc/amd/common/block/acp/acp.c
@@ -5,47 +5,13 @@
 #include <amdblocks/acp.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/chip.h>
-#include <console/console.h>
 #include <device/device.h>
-#include <device/mmio.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <commonlib/helpers.h>
+#include "acp_def.h"
 
-/* ACP registers and associated fields */
-#define ACP_I2S_PIN_CONFIG	0x1400	/* HDA, Soundwire, I2S */
-#define  PIN_CONFIG_MASK	(7 << 0)
-#define ACP_I2S_WAKE_EN		0x1414
-#define  WAKE_EN_MASK		(1 << 0)
-#define ACP_PME_EN		0x1418
-#define  PME_EN_MASK		(1 << 0)
-
-static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set)
-{
-	clrsetbits32((void *)(bar + reg), clear, set);
-}
-
-static void init(struct device *dev)
-{
-	const struct soc_amd_common_config *cfg = soc_get_common_config();
-	struct resource *res;
-	uintptr_t bar;
-
-	res = dev->resource_list;
-	if (!res || !res->base) {
-		printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__);
-		return;
-	}
-
-	/* Set the proper I2S_PIN_CONFIG state */
-	bar = (uintptr_t)res->base;
-	acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_config.acp_pin_cfg);
-
-	/* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */
-	acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_config.acp_i2s_wake_enable);
-	acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_config.acp_pme_enable);
-}
 
 static const char *acp_acpi_name(const struct device *dev)
 {
@@ -78,7 +44,7 @@ static struct device_operations acp_ops = {
 	.read_resources = pci_dev_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init = init,
+	.init = acp_init,
 	.ops_pci = &pci_dev_ops_pci,
 	.scan_bus = scan_static_bus,
 	.acpi_name = acp_acpi_name,
diff --git a/src/soc/amd/common/block/acp/acp_def.h b/src/soc/amd/common/block/acp/acp_def.h
new file mode 100644
index 0000000000..55af01aa02
--- /dev/null
+++ b/src/soc/amd/common/block/acp/acp_def.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __AMD_ACP_DEF_H__
+#define __AMD_ACP_DEF_H__
+
+/* This command needs to be implemented by the generation specific code. */
+void acp_init(struct device *dev);
+
+#endif /* __AMD_ACP_DEF_H__ */
diff --git a/src/soc/amd/common/block/acp/acp_gen1.c b/src/soc/amd/common/block/acp/acp_gen1.c
new file mode 100644
index 0000000000..0fe37f3806
--- /dev/null
+++ b/src/soc/amd/common/block/acp/acp_gen1.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acp.h>
+#include <amdblocks/chip.h>
+#include <device/device.h>
+#include <device/mmio.h>
+#include <console/console.h>
+#include "acp_def.h"
+
+/* ACP registers and associated fields */
+#define ACP_I2S_PIN_CONFIG	0x1400	/* HDA, Soundwire, I2S */
+#define  PIN_CONFIG_MASK	(7 << 0)
+#define ACP_I2S_WAKE_EN		0x1414
+#define  WAKE_EN_MASK		(1 << 0)
+#define ACP_PME_EN		0x1418
+#define  PME_EN_MASK		(1 << 0)
+
+static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set)
+{
+	clrsetbits32((void *)(bar + reg), clear, set);
+}
+
+void acp_init(struct device *dev)
+{
+	const struct soc_amd_common_config *cfg = soc_get_common_config();
+	struct resource *res;
+	uintptr_t bar;
+
+	res = dev->resource_list;
+	if (!res || !res->base) {
+		printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__);
+		return;
+	}
+
+	/* Set the proper I2S_PIN_CONFIG state */
+	bar = (uintptr_t)res->base;
+	acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_config.acp_pin_cfg);
+
+	/* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */
+	acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_config.acp_i2s_wake_enable);
+	acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_config.acp_pme_enable);
+}