diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-04-09 11:50:48 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-10 20:22:27 +0000 |
| commit | 65b0afe9a687aebeed70eccd78e1ad99b96bc8bc (patch) | |
| tree | de861f60afbb85cc5b49f0ff5334b4120f3683ba /src/soc/amd/common | |
| parent | 6ada39e790a4f7ea2e5d1b74a27c2e7b68a6115d (diff) | |
soc/amd/cezanne: Add GRXS and GTXS method
Add GRXS and GTXS support. Move the gpio method into common place.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/acpi/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/amd/common/block/acpi/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/acpi/gpio.c | 52 |
3 files changed, 56 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig index 024b378e68..716610e370 100644 --- a/src/soc/amd/common/block/acpi/Kconfig +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -4,3 +4,6 @@ config SOC_AMD_COMMON_BLOCK_ACPI select ACPI_AMD_HARDWARE_SLEEP_VALUES help Select this option to use the AcpiMmio ACPI registers. + +config SOC_AMD_COMMON_BLOCK_ACPI_GPIO + bool diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index 3f5d47a1ff..1bec9e57a1 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -9,5 +9,6 @@ smm-y += acpi.c ramstage-y += pm_state.c ramstage-y += tables.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO) += gpio.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPI diff --git a/src/soc/amd/common/block/acpi/gpio.c b/src/soc/amd/common/block/acpi/gpio.c new file mode 100644 index 0000000000..15ee292e7d --- /dev/null +++ b/src/soc/amd/common/block/acpi/gpio.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <console/console.h> +#include <soc/gpio.h> + +static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + if (gpio_num >= SOC_GPIO_TOTAL_PINS) { + printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" + " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); + return -1; + } + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + +static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) +{ + if (gpio_num >= SOC_GPIO_TOTAL_PINS) { + printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" + " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); + return -1; + } + /* Store (op (gpio_num), Local0) */ + acpigen_write_store(); + acpigen_soc_gpio_op(op, gpio_num); + acpigen_emit_byte(LOCAL0_OP); + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.GRXS", gpio_num); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.GTXS", gpio_num); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.STXS", gpio_num); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.CTXS", gpio_num); +} |