diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-24 20:33:15 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-29 16:17:56 +0000 |
| commit | 60df7ca07b2c244ce23cd08867683e49e6361f87 (patch) | |
| tree | b9f527e308f361f6a4ae6760d5bd996a6a7800d0 /src/soc/amd/common | |
| parent | 56f1221f2fd00d27fedb6de9f8501127e66f5878 (diff) | |
soc/amd/common/block/cpu/Kconfig: drop FAM17H_19H suffix from TSC option
The SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H option is valid for all SoCs
with Zen-based CPU cores including the family 1Ah, so remove the suffix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I58d29e69a44b7b97fa5cfeb0e461531b926f7480
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/cpu/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/tsc/Makefile.inc | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 056e133f41..5a1f86a6fa 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -96,15 +96,15 @@ config SOC_AMD_COMMON_BLOCK_SVI3 Select this option is the SoC uses the serial VID 3 standard for encoding the voltage it requests from the VRM. -config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H +config SOC_AMD_COMMON_BLOCK_TSC bool select COLLECT_TIMESTAMPS_NO_TSC # selected use SoC-specific timestamp function select TSC_SYNC_LFENCE select UDELAY_TSC help Select this option to add the common functions for getting the TSC - frequency of AMD family 17h and 19h CPUs/APUs and to provide TSC- - based monotonic timer functionality to the build. + frequency of AMD family 17h, 19h and 1Ah CPUs/APUs and to provide + TSC-based monotonic timer functionality to the build. config SOC_AMD_COMMON_BLOCK_UCODE bool diff --git a/src/soc/amd/common/block/cpu/tsc/Makefile.inc b/src/soc/amd/common/block/cpu/tsc/Makefile.inc index 77bdf77886..67bd6fbaeb 100644 --- a/src/soc/amd/common/block/cpu/tsc/Makefile.inc +++ b/src/soc/amd/common/block/cpu/tsc/Makefile.inc @@ -20,7 +20,7 @@ smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H),y) +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_TSC),y) bootblock-y += tsc_freq.c bootblock-y += monotonic_timer.c @@ -37,4 +37,4 @@ ramstage-y += monotonic_timer.c smm-y += tsc_freq.c smm-y += monotonic_timer.c -endif # CONFIG_SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H +endif # CONFIG_SOC_AMD_COMMON_BLOCK_TSC |