diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-13 01:24:38 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-14 14:59:59 +0000 |
| commit | b82cafad9353c135fa0e67141c80f3af4f6c0c1e (patch) | |
| tree | 7fc83a12486b6525ac6e61cfe1ed6a02ee4598c8 /src/soc/amd/common | |
| parent | c2d01122001477613881808fd23c9870ed5ecf17 (diff) | |
soc/amd/picasso: remove broken and unused legacy UART support
The UARTs in the Picasso SoC are memory mapped, but there is also some
hardware support that isn't used by any board to make the UARTs behave
like the ones found on legacy x86 machines from the 90s.
In the MMIO mode the MMIO address of the UART controller is passed to
the OS via ACPI. The OS expects the base clock of the UART controller to
be 48MHz (see the cz_uart_desc struct in drivers/acpi/acpi_apd.c and
drivers/tty/serial/8250/8250_dw.c in the Linux kernel) in this case. It
is also possible to enable additional decodes from four 8 byte legacy
I/O locations used for serial ports to the different UART controllers,
which doesn't disable the MMIO access though. The legacy I/O-mapped
serial ports are usually expected to have a base clock of 16*115200Hz
which the hardware can also provide to the UART's baud rate generator.
So there are two possible valid configurations to use the UARTs; either
MMIO access in combination with a 48MHz base clock or the legacy I/O
decode with a ~1.8MHz base clock.
The existing code unconditionally generates ACPI objects for all enabled
UARTs, so those shouldn't be put into legacy mode and switching the base
clock to ~1.8MHz was only done in the case that the UART was used as
coreboot console UART which still used the MMIO access, but the lower
base clock. Since no board even selects this option and it's rather
invasive to properly implement this feature, just drop the corresponding
broken code.
TEST=SoC UART console still works on Mandolin.
Change-Id: I26fa8fdfc781b583ba56ac4dbcbbfb6100e84852
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/uart/Kconfig | 25 | ||||
| -rw-r--r-- | src/soc/amd/common/block/uart/uart_console.c | 2 |
2 files changed, 1 insertions, 26 deletions
diff --git a/src/soc/amd/common/block/uart/Kconfig b/src/soc/amd/common/block/uart/Kconfig index 599594ba5e..c348187260 100644 --- a/src/soc/amd/common/block/uart/Kconfig +++ b/src/soc/amd/common/block/uart/Kconfig @@ -21,31 +21,6 @@ config AMD_SOC_CONSOLE_UART 2: 0xfedc3000 3: 0xfedcf000 -choice - prompt "UART Frequency" - depends on AMD_SOC_CONSOLE_UART - default AMD_SOC_UART_48MZ - -config AMD_SOC_UART_48MZ - bool "48 MHz clock" - help - Select this option for the most compatibility. - -config AMD_SOC_UART_1_8MZ - bool "1.8432 MHz clock" - help - Select this option if an old payload or Linux ttyS0 arguments require - a 1.8432 MHz clock source for the UART. - -endchoice - -config AMD_SOC_UART_LEGACY - bool "Decode legacy I/O range" - help - Assign I/O 3F8, 2F8, etc. to an integrated AMD SoC UART. A UART - accessed with I/O does not allow all the features of MMIO. The MMIO - decode is still present when this option is used. - config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART hex diff --git a/src/soc/amd/common/block/uart/uart_console.c b/src/soc/amd/common/block/uart/uart_console.c index c1c17232fb..ff9122fbe4 100644 --- a/src/soc/amd/common/block/uart/uart_console.c +++ b/src/soc/amd/common/block/uart/uart_console.c @@ -15,5 +15,5 @@ uintptr_t uart_platform_base(unsigned int idx) unsigned int uart_platform_refclk(void) { - return CONFIG(AMD_SOC_UART_48MZ) ? 48000000 : 115200 * 16; + return 48000000; } |