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authorFelix Held <felix-coreboot@felixheld.de>2021-02-11 03:01:18 +0100
committerMartin Roth <martinroth@google.com>2021-02-12 20:48:28 +0000
commit1b33205909c5a8f775eefd19107406a620a7fcc5 (patch)
tree582707c548758a3cd8f922f8ac97688652a57305 /src/soc/amd/common
parent428a682abe7a0aaf1414d6c9d4f6c862f4c2b5fe (diff)
soc/amd/common: add and use fch_enable_ioapic_decode
The default value of this bit is 0, so set it right before calling setup_ioapic to make sure that it's set and not to have to rely on FSP doing the right thing. Change-Id: Ife886451a6927965769282fc5644c2085abb9585 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50513 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common')
-rw-r--r--src/soc/amd/common/block/acpimmio/mmio_util.c5
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio.h2
-rw-r--r--src/soc/amd/common/block/smbus/sm.c1
3 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c
index 1cacd44433..a19a28bd0e 100644
--- a/src/soc/amd/common/block/acpimmio/mmio_util.c
+++ b/src/soc/amd/common/block/acpimmio/mmio_util.c
@@ -74,6 +74,11 @@ void fch_io_enable_legacy_io(void)
pm_io_write32(PM_DECODE_EN, pm_io_read32(PM_DECODE_EN) | LEGACY_IO_EN);
}
+void fch_enable_ioapic_decode(void)
+{
+ pm_write32(PM_DECODE_EN, pm_read32(PM_DECODE_EN) | FCH_IOAPIC_EN);
+}
+
/* PM registers are accessed a byte at a time via CD6/CD7 */
uint8_t pm_io_read8(uint8_t reg)
{
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 4b80a28a0d..19decdd81b 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -17,6 +17,7 @@
#define PM_DECODE_EN 0x00
#define SMBUS_ASF_IO_BASE_SHIFT 8
#define SMBUS_ASF_IO_BASE_MASK (0xff << SMBUS_ASF_IO_BASE_SHIFT)
+#define FCH_IOAPIC_EN (1 << 5)
#define SMBUS_ASF_IO_EN (1 << 4)
#define CF9_IO_EN (1 << 1)
#define LEGACY_IO_EN (1 << 0)
@@ -75,6 +76,7 @@ void enable_acpimmio_decode_pm04(void);
void fch_enable_cf9_io(void);
void fch_enable_legacy_io(void);
void fch_io_enable_legacy_io(void);
+void fch_enable_ioapic_decode(void);
/* Access PM registers using IO cycles */
uint8_t pm_io_read8(uint8_t reg);
diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c
index 1ec2730561..0b219e006d 100644
--- a/src/soc/amd/common/block/smbus/sm.c
+++ b/src/soc/amd/common/block/smbus/sm.c
@@ -11,6 +11,7 @@
static void sm_init(struct device *dev)
{
+ fch_enable_ioapic_decode();
setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
}