diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-11-24 10:54:20 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-25 18:45:53 +0000 |
| commit | f80f32b0e5b183f5ef269b94598dcef58a73a657 (patch) | |
| tree | 38d8e658c2c2558f987d7c37d1142ffd64137a67 /src/soc/amd/common | |
| parent | 23d03e912ae8d3e4b2e0d446d6a447b71825dd73 (diff) | |
soc/amd/common/aoac: fix typo in FCH_AOAC_REF_CLK_OK_STATE definition
The bit is called REF_CLK_OK_STATE and not RST_CLK_OK_STATE, so change
the name of the define to FCH_AOAC_REF_CLK_OK_STATE.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iae26db94d83ebb2cb799f6d3e0bec37c8e849219
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/aoac/aoac.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/aoac.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/amd/common/block/aoac/aoac.c b/src/soc/amd/common/block/aoac/aoac.c index c5f161bfcb..0afd2a1f19 100644 --- a/src/soc/amd/common/block/aoac/aoac.c +++ b/src/soc/amd/common/block/aoac/aoac.c @@ -24,8 +24,8 @@ void power_off_aoac_device(unsigned int dev) bool is_aoac_device_enabled(unsigned int dev) { uint8_t byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); - byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); - if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) + byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_REF_CLK_OK_STATE); + if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_REF_CLK_OK_STATE)) return true; else return false; diff --git a/src/soc/amd/common/block/include/amdblocks/aoac.h b/src/soc/amd/common/block/include/amdblocks/aoac.h index ff5d0db169..f4a00c73a7 100644 --- a/src/soc/amd/common/block/include/amdblocks/aoac.h +++ b/src/soc/amd/common/block/include/amdblocks/aoac.h @@ -24,7 +24,7 @@ /* Bit definitions for Device D3 State AOACx0000[41...7f; odd byte addresses] */ #define FCH_AOAC_PWR_RST_STATE BIT(0) -#define FCH_AOAC_RST_CLK_OK_STATE BIT(1) +#define FCH_AOAC_REF_CLK_OK_STATE BIT(1) #define FCH_AOAC_RST_B_STATE BIT(2) #define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3) #define FCH_AOAC_D3COLD BIT(4) |