diff options
| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2023-02-20 09:43:38 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-02 13:06:09 +0000 |
| commit | eede5a24959139639a0156ccb3795d1468e996bc (patch) | |
| tree | ea4cc006139d643d9e20456cfd2404baced3acc3 /src/soc/amd/common | |
| parent | 9edaccd922af346bba59ce32668fd91f051af1d6 (diff) | |
soc/amd/mendocino: Add new 'STT_ALPHA_APU' parameter for DPTC support
Add a new parameter STT_ALPHA_APU' for each DPTC mode.
BUG=b:257149501
BRANCH=None
TEST=Check if the STT value matches the expected setting.
Change-Id: Ib27572712d57585f66030d9e927896a8249e97a7
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/alib.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h index 82d69358a3..3cae027c61 100644 --- a/src/soc/amd/common/block/include/amdblocks/alib.h +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -21,6 +21,7 @@ enum alib_dptc_parameter_ids { /* Picasso: SetVrmSocCurrentLimit (0xe) is not implemented in alib. */ ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID = 0xe, + ALIB_DPTC_STT_ALPHA_APU = 0x20, ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID = 0x22, ALIB_DPTC_STT_M1_ID = 0x26, ALIB_DPTC_STT_M2_ID = 0x27, |