diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-03-03 22:37:34 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-06 17:20:45 +0000 |
| commit | cbe55a1728e4f5f3c46e92754fb098aab85fbe91 (patch) | |
| tree | 2b5abe4eaaf5735291f78d49273180e672087c15 /src/soc/amd/common | |
| parent | c8755141c0849fad536ec12451230f0fd4a6a62a (diff) | |
soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs
The legacy ACPI CPU control registers in IO space where the first 4 IO
locations control the CPU throttling value don't exist any more on the
Zen-based CPUs. Instead this IO address is written to MSR_CSTATE_ADDRESS
in set_cstate_io_addr which will cause accesses from the 8 IO addresses
beginning with ACPI_CSTATE_CONTROL to be trapped in the CPU core. Reads
from those IO addresses will cause the CPU to enter low C states.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index 8fd371564e..8151b964d0 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -24,6 +24,6 @@ void set_cstate_io_addr(void) msr_t cst_addr; cst_addr.hi = 0; - cst_addr.lo = ACPI_CPU_CONTROL; + cst_addr.lo = ACPI_CSTATE_CONTROL; wrmsr(MSR_CSTATE_ADDRESS, cst_addr); } |