diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-11-07 16:23:53 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-27 16:45:36 +0000 |
| commit | 9ec60411ac999b342296fb10785aac44bbb4d6bb (patch) | |
| tree | 012448553648629a9f51e46565ecba2c01efddef /src/soc/amd/common | |
| parent | 01816e6a4f1848c89bccaea0bb87affc8c2b1f90 (diff) | |
soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params
This commit separates setting FSP debug params from the rest of code and
configures FSP serial port parameters. Other ports (0x3E8 and 0x2E8)
are omitted since Elkhart Lake FSP only supports 0x3F8 and 0x2F8.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I84f7c19a7c2fd5a4db18f5a37e1c667da017aace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/soc/amd/common')
0 files changed, 0 insertions, 0 deletions