diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-12-04 19:51:17 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-09 14:23:43 +0000 |
| commit | b3621f811d226c322fc6b21b583270c6b40e7e4c (patch) | |
| tree | 5342e8dfbd3b1ae7c9f7d899c86d87836734ed5f /src/soc/amd/common | |
| parent | 8d187f4d22572fa01dabd46d994b3639eb83b382 (diff) | |
soc/amd: Remove Kconfig BOOTBLOCK_ADDR
Due the location of X86_RESET_VECTOR, the anchor point
for linking the bootblock is at the end, which equals
ROMSTAGE_ADDR.
Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index dae69d030f..f702b4b201 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -10,6 +10,9 @@ #define PSP_SHAREDMEM_DRAM_START(addr) SYMBOL(psp_sharedmem_dram, addr) #define PSP_SHAREDMEM_DRAM_END(addr) SYMBOL(epsp_sharedmem_dram, addr) +BOOTBLOCK_END = CONFIG_ROMSTAGE_ADDR; +BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; + /* * * +--------------------------------+ @@ -31,11 +34,11 @@ * +--------------------------------+ FSP_M_ADDR * | romstage | * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR - * | | X86_RESET_VECTOR = BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 * | bootblock | * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE * | Unused hole | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | @@ -84,8 +87,8 @@ SECTIONS #if CONFIG(VBOOT) PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif - _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); - BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) + _ = ASSERT(BOOTBLOCK_END == ((BOOTBLOCK_END + 0xFFFF) & 0xFFFF0000), "Bootblock end must be 16 bit aligned"); + BOOTBLOCK(BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE) REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) #if CONFIG(VBOOT_SEPARATE_VERSTAGE) @@ -107,7 +110,7 @@ SECTIONS { _TOO_LOW = _X86_RESET_VECTOR - 0xfff0; _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); - . = CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10; + . = BOOTBLOCK_END - 0x10; _X86_RESET_VECTOR = .; .reset . : { *(.reset); |