diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-09 21:36:56 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-11 00:43:16 +0000 |
| commit | 6f8f9c969be9d471464f1b6a42b4bb1c2590db5c (patch) | |
| tree | 87dcfda6643117932f9f926e3f17d44e41fa1ec4 /src/soc/amd/common | |
| parent | 0dfaf33a1331ede41c052be20217abcf2b70e141 (diff) | |
soc/amd/picasso: move UART Kconfig options to common folder
The actual UART initialization code will be factored out in follow-up
commits.
Change-Id: Ie4ddf1951b230323c5480c4389376c62dd74b0e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/uart/Kconfig | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/uart/Kconfig b/src/soc/amd/common/block/uart/Kconfig new file mode 100644 index 0000000000..599594ba5e --- /dev/null +++ b/src/soc/amd/common/block/uart/Kconfig @@ -0,0 +1,57 @@ +config SOC_AMD_COMMON_BLOCK_UART + bool + default n + help + Select this option to add the common functions for setting up the + UART configuration to the build. + +if SOC_AMD_COMMON_BLOCK_UART + +config AMD_SOC_CONSOLE_UART + bool "Use integrated AMD SoC UART controller for console" + default n + select DRIVERS_UART_8250MEM + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + select UART_OVERRIDE_REFCLK + help + There are four memory-mapped UARTs controllers at: + 0: 0xfedc9000 + 1: 0xfedca000 + 2: 0xfedc3000 + 3: 0xfedcf000 + +choice + prompt "UART Frequency" + depends on AMD_SOC_CONSOLE_UART + default AMD_SOC_UART_48MZ + +config AMD_SOC_UART_48MZ + bool "48 MHz clock" + help + Select this option for the most compatibility. + +config AMD_SOC_UART_1_8MZ + bool "1.8432 MHz clock" + help + Select this option if an old payload or Linux ttyS0 arguments require + a 1.8432 MHz clock source for the UART. + +endchoice + +config AMD_SOC_UART_LEGACY + bool "Decode legacy I/O range" + help + Assign I/O 3F8, 2F8, etc. to an integrated AMD SoC UART. A UART + accessed with I/O does not allow all the features of MMIO. The MMIO + decode is still present when this option is used. + +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART + hex + default 0xfedc9000 if UART_FOR_CONSOLE = 0 + default 0xfedca000 if UART_FOR_CONSOLE = 1 + default 0xfedc3000 if UART_FOR_CONSOLE = 2 + default 0xfedcf000 if UART_FOR_CONSOLE = 3 + +endif # SOC_AMD_COMMON_BLOCK_UART |