diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-10 00:06:12 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-11 00:44:31 +0000 |
| commit | 8485637287a93095dc3d51725ad7be033af257cb (patch) | |
| tree | 9080fe7f0fe3b47be07bd294f44d5d4288bd4d9c /src/soc/amd/common | |
| parent | d3e977112a6b07d372e36667dbe8f9c8fe5c30f7 (diff) | |
soc/amd/picasso: factor out write_resume_eip to common code
Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/common')
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/write_resume_eip.c | 27 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/cpu.h | 8 |
3 files changed, 36 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc index 7a3be34782..ed08d2a1c4 100644 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y) bootblock-y += pre_c.S +bootblock-y += write_resume_eip.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c b/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c new file mode 100644 index 0000000000..d53916107e --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/cpu.h> +#include <amdblocks/cpu.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/msr.h> +#include <stdint.h> + +asmlinkage void bootblock_resume_entry(void); + +void write_resume_eip(void) +{ + msr_t s3_resume_entry = { + .hi = (uint64_t)(uintptr_t)bootblock_resume_entry >> 32, + .lo = (uintptr_t)bootblock_resume_entry & 0xffffffff, + }; + + /* + * Writing to the EIP register can only be done once, otherwise a fault is triggered. + * When this register is written, it will trigger the microcode to stash the CPU state + * (crX , mtrrs, registers, etc) into the CC6 save area. On resume, the state will be + * restored and execution will continue at the EIP. + */ + if (!acpi_is_wakeup_s3()) + wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); +} diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h new file mode 100644 index 0000000000..0a93643e2a --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_CPU_H +#define AMD_BLOCK_CPU_H + +void write_resume_eip(void); + +#endif /* AMD_BLOCK_CPU_H */ |