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authorFelix Held <felix-coreboot@felixheld.de>2024-01-18 21:43:30 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-01-20 01:28:01 +0000
commit4e818c5309d1efc79dad2771eaae0c37e6a07315 (patch)
treec6d380efa136889da4a6c444779eb5d6759b786f /src/soc/amd/common/fsp
parentce60fb1d6305744ea7655c57b1c1efbf8451a6bc (diff)
soc/amd/*/chip: factor out FSP-S call
Move the call into the FSP code to a file in the common AMD FSP code to isolate the FSP-specific parts of the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic8236db7ac80275a65020b7e7a9acce8314c831c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/common/fsp')
-rw-r--r--src/soc/amd/common/fsp/Makefile.inc1
-rw-r--r--src/soc/amd/common/fsp/fsp_ramstage.c9
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/amd/common/fsp/Makefile.inc b/src/soc/amd/common/fsp/Makefile.inc
index 2517f0c6fe..fb78f52925 100644
--- a/src/soc/amd/common/fsp/Makefile.inc
+++ b/src/soc/amd/common/fsp/Makefile.inc
@@ -6,6 +6,7 @@ romstage-y += fsp_romstage.c
romstage-y += fsp_validate.c
ramstage-y += fsp_graphics.c
ramstage-y += fsp_memmap.c
+ramstage-y += fsp_ramstage.c
ramstage-y += fsp_report_resources.c
ramstage-y += fsp_reset.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fsp-acpi.c
diff --git a/src/soc/amd/common/fsp/fsp_ramstage.c b/src/soc/amd/common/fsp/fsp_ramstage.c
new file mode 100644
index 0000000000..f329e98e46
--- /dev/null
+++ b/src/soc/amd/common/fsp/fsp_ramstage.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/fsp.h>
+#include <fsp/api.h>
+
+void amd_fsp_silicon_init(void)
+{
+ fsp_silicon_init();
+}