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authorFelix Held <felix-coreboot@felixheld.de>2024-04-19 18:35:15 +0200
committerFelix Held <felix-coreboot@felixheld.de>2024-04-24 21:25:49 +0000
commit2ec63b54d8cb5193aba548bc8f78622112a656d6 (patch)
tree409a0c0f2805d2e213cbae04dd105e6beaa38077 /src/soc/amd/common/fsp
parent6ad7513e03952c32650988d2a825f4f1661d5ee9 (diff)
soc/amd/common/amd_pci_util.h: rename bridge irq in pci_routing_info
Rename the 'irq' element of the pci_routing_info struct to 'bridge_irq' to better describe what it's doing. This struct element contains the number of the northbridge IOAPIC IRQ input the bridge IRQ is connected to signal power management or error reporting IRQs. Right now, coreboot doesn't put this information into the ACPI bytecode. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6410be673d15d6f9b5eb4c80b51fb705fec5b155 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/common/fsp')
-rw-r--r--src/soc/amd/common/fsp/pci/pci_routing_info.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/common/fsp/pci/pci_routing_info.c b/src/soc/amd/common/fsp/pci/pci_routing_info.c
index 5e3c368c0f..96ea1ff872 100644
--- a/src/soc/amd/common/fsp/pci/pci_routing_info.c
+++ b/src/soc/amd/common/fsp/pci/pci_routing_info.c
@@ -34,9 +34,9 @@ const struct pci_routing_info *get_pci_routing_table(size_t *entries)
routing_table_entries = routing_hob->num_of_entries;
for (size_t i = 0; i < routing_table_entries; ++i) {
- printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, irq: %u\n",
+ printk(BIOS_DEBUG, "%02x.%x: group: %u, swizzle: %u, bridge irq: %u\n",
PCI_SLOT(routing_table[i].devfn), PCI_FUNC(routing_table[i].devfn),
- routing_table[i].group, routing_table[i].swizzle, routing_table[i].irq);
+ routing_table[i].group, routing_table[i].swizzle, routing_table[i].bridge_irq);
}
*entries = routing_table_entries;