soc/amd: add PSP SMI handler stub

The PSP can send SMIs to the x86 side to have the SMI handler service
requests from the PSP. This commit adds an empty PSP SMI handler; the
actual implementation is added in later patches to keep the patches
relatively small.

This patch is a slightly modified version of parts of CB:65523.

Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Change-Id: I65989ff529d728cd9d2cd60b384295417bef77ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83739
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 38 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h
index abdb762af8..061e79def5 100644
--- a/src/soc/amd/common/block/include/amdblocks/psp.h
+++ b/src/soc/amd/common/block/include/amdblocks/psp.h
@@ -57,6 +57,12 @@ int psp_notify_dram(void);
 
 int psp_notify_smm(void);
 
+#if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI))
+void psp_smi_handler(void);
+#else
+static inline void psp_smi_handler(void) {}
+#endif
+
 /*
  * type: identical to the corresponding PSP command, e.g. pass
  *       MBOX_BIOS_CMD_SMU_FW2 to load SMU FW2 blob.
diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig
index 266a6ba10e..34a0642893 100644
--- a/src/soc/amd/common/block/psp/Kconfig
+++ b/src/soc/amd/common/block/psp/Kconfig
@@ -88,6 +88,25 @@ config PSP_PLATFORM_SECURE_BOOT
 	  Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is
 	  only available with NDA customers.
 
+config SOC_AMD_COMMON_BLOCK_PSP_SMI
+	bool
+	default n
+	select SPI_FLASH_SMM if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP
+	help
+	  Add PSP SMI handler for SPI flash access.
+
+	  When ROM armor isn't enabled, the x86 part owns the SPI controller,
+	  so when the PSP wants to access the SPI flash, it sends an SMI to the
+	  x86 side and the corresponding SMI handler will do the SPI flash
+	  access for the PSP.
+
+	  WARNING: Since the flash access in the SMI handler is a blocking
+	  operation during which all cores stay in SMM, an erase operation may
+	  lock up the system for a long enough time to be noticeable. Reads and
+	  writes with small data sizes are less problematic. This is AMD
+	  specific design and should be enabled when PSP requires to access the
+	  SPI flash after the BOOT_DONE PSP command.
+
 config PSP_INCLUDES_HSP
 	bool
 	depends on SOC_AMD_COMMON_BLOCK_PSP
diff --git a/src/soc/amd/common/block/psp/Makefile.mk b/src/soc/amd/common/block/psp/Makefile.mk
index d0fbcbe452..c16a73b698 100644
--- a/src/soc/amd/common/block/psp/Makefile.mk
+++ b/src/soc/amd/common/block/psp/Makefile.mk
@@ -4,6 +4,7 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP),y)
 romstage-y += psp.c
 ramstage-y += psp.c
 smm-y += psp.c
+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_SMI) += psp_smi.c
 smm-y += psp_smm.c
 
 bootblock-y += psp_efs.c
diff --git a/src/soc/amd/common/block/psp/psp_smi.c b/src/soc/amd/common/block/psp/psp_smi.c
new file mode 100644
index 0000000000..b94366ca5a
--- /dev/null
+++ b/src/soc/amd/common/block/psp/psp_smi.c
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/psp.h>
+
+void psp_smi_handler(void)
+{
+}
diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c
index f3b90ae81e..4f76ebc421 100644
--- a/src/soc/amd/common/block/psp/psp_smm.c
+++ b/src/soc/amd/common/block/psp/psp_smm.c
@@ -6,6 +6,7 @@
 #include <region_file.h>
 #include <console/console.h>
 #include <amdblocks/psp.h>
+#include <amdblocks/smi.h>
 #include <soc/iomap.h>
 #include <string.h>
 
@@ -89,6 +90,10 @@ int psp_notify_smm(void)
 	soc_fill_smm_reg_info(&buffer.req.smm_reg_info);
 #endif
 
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) {
+		configure_psp_smi();
+	}
+
 	printk(BIOS_DEBUG, "PSP: Notify SMM info... ");
 
 	cmd_status = send_psp_command_smm(MBOX_BIOS_CMD_SMM_INFO, &buffer);