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authorJamie Chen <jamie_chen@compal.corp-partner.google.com>2023-05-02 13:32:42 +0800
committerMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-05-03 16:08:12 +0000
commit22b226724e71822d81d142a866f892dd0949e954 (patch)
tree55f82a8cbc8b8bf92cc4ee5d5e8f7fa67dc47731 /src/soc/amd/common/block
parent50931f8ea0f450981b354f6d24d7e013c79d8ff4 (diff)
mb/google/brya/var/omnigul: Adjust I2C3 and I2C5 Waveform meet to SPEC
Tuning i2c frequency ,timing ,Waveform meet to SPEC i2c frequency : I2C0=>399.8khz / Setup Time:1765ns / Hold Time:82.35ns. I2C1=>390.4khz / Setup Time:1.788us / Hold Time:70.58ns. I2C3=>308.7khz / Setup Time:1.482us / Hold Time:0.4us. I2C5=>390.8khz / Setup Time:1.218us / Hold Time:0.405us. BUG=b:275061994 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, EE check OK with test FW and TP function is normal. Change-Id: I5b77cd3fd3ff00804f1b8dd5828dc831a9732566 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74880 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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