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| author | Edward O'Callaghan <quasisec@google.com> | 2020-06-24 09:45:49 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-06-30 21:19:23 +0000 |
| commit | 811284125f0a553963de0e849b18cf60b66be5c4 (patch) | |
| tree | 813515c23e3478be91d602f73ae7f9f36cf50a10 /src/soc/amd/common/block | |
| parent | f4a940c23613b988512f46acf45b4e0eb338e2c5 (diff) | |
soc/intel/cannonlake: Add UWES ASL into xhci.asl
Align support for enable wake-on-usb attach/detach as was
introduced in Skylake in
`commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`.
This adds the USB Wake Enable Setup (UWES) ASL blocks
required to inform the OS about plug wake events bits
being set in the PORTSCN register configured by devicetree.
BUG=b:159187889
BRANCH=none
TEST=none
Change-Id: I6c63d226e5acadff04486c8a6764fb715a0ac051
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/amd/common/block')
0 files changed, 0 insertions, 0 deletions