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authorRaul E Rangel <rrangel@chromium.org>2022-04-25 13:32:35 -0600
committerFelix Held <felix-coreboot@felixheld.de>2022-04-27 11:33:00 +0000
commitdbeae6ab008cc0062bdc17bde1aa5dd1b1fd14a5 (patch)
treeb1c393b7a516ccc2e6640667cc640458d126fc90 /src/soc/amd/common/block
parentd0dc50cf6b514c3260cb423088eb56172da1c992 (diff)
soc/amd/common/block/lpc/espi: Add support for ALERT_ENABLE bit
This bit is new on sabrina. We need to enable it after initialization has completed. BUG=b:227282870 TEST=Boot skyrim to OS and verify keyboard works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I795275993589e20c1d09674232ecff782c491335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/amd/common/block')
-rw-r--r--src/soc/amd/common/block/lpc/Kconfig6
-rw-r--r--src/soc/amd/common/block/lpc/espi_def.h1
-rw-r--r--src/soc/amd/common/block/lpc/espi_util.c11
3 files changed, 15 insertions, 3 deletions
diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig
index 125f8b326a..b1db1bd254 100644
--- a/src/soc/amd/common/block/lpc/Kconfig
+++ b/src/soc/amd/common/block/lpc/Kconfig
@@ -36,6 +36,12 @@ config SOC_AMD_COMMON_BLOCK_HAS_ESPI
Select this option if platform supports eSPI using D14F3 configuration
registers.
+config SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE
+ bool
+ depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI
+ help
+ Selected by the SoC if it supports the ALERT_ENABLE bit.
+
config SOC_AMD_COMMON_BLOCK_USE_ESPI
bool
depends on SOC_AMD_COMMON_BLOCK_HAS_ESPI
diff --git a/src/soc/amd/common/block/lpc/espi_def.h b/src/soc/amd/common/block/lpc/espi_def.h
index a14f10fac6..ef61a13929 100644
--- a/src/soc/amd/common/block/lpc/espi_def.h
+++ b/src/soc/amd/common/block/lpc/espi_def.h
@@ -25,6 +25,7 @@
#define ESPI_WDG_EN (1 << 0)
#define ESPI_GLOBAL_CONTROL_1 0x34
+#define ESPI_ALERT_ENABLE (1 << 20) /* Sabrina and later SoCs */
#define ESPI_RGCMD_INT_MAP_SHIFT 13
#define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT)
#define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT)
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 68d51f5ba0..c4d15e4b70 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -936,7 +936,7 @@ static void espi_setup_subtractive_decode(const struct espi_config *mb_cfg)
enum cb_err espi_setup(void)
{
- uint32_t slave_caps;
+ uint32_t slave_caps, ctrl;
const struct espi_config *cfg = espi_get_config();
printk(BIOS_SPEW, "Initializing ESPI.\n");
@@ -1035,8 +1035,13 @@ enum cb_err espi_setup(void)
/* Enable subtractive decode if configured */
espi_setup_subtractive_decode(cfg);
- espi_write32(ESPI_GLOBAL_CONTROL_1,
- espi_read32(ESPI_GLOBAL_CONTROL_1) | ESPI_BUS_MASTER_EN);
+ ctrl = espi_read32(ESPI_GLOBAL_CONTROL_1);
+ ctrl |= ESPI_BUS_MASTER_EN;
+
+ if (CONFIG(SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE))
+ ctrl |= ESPI_ALERT_ENABLE;
+
+ espi_write32(ESPI_GLOBAL_CONTROL_1, ctrl);
printk(BIOS_SPEW, "Finished initializing ESPI.\n");