soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK

Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build.  The .S files
are mostly duplicated code from the old cache_as_ram.inc file.

The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.

Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S.  Drop the BIST check like other devices.

Move InitReset and InitEarly to bootblock.  These AGESA entry
points set some default settings, and release/recapture the
AP cores.  There are currently some early dependencies on
InitReset.  Future work should include:
 * Pull the necessary functionality from InitReset into bootblock
 * Move InitReset and InitEarly to car_stage_entry() and out of
   bootblock
   - Add a mechanism for the BSP to give the APs an address
     to call and skip most of bootblock and verstage (when
     available) (1)
   - Reunify BiosCallOuts.c and OemCustomize.c

(1) During the InitReset call, the BSP enables the APs by setting
    core enable bits in F18F0x1DC and APs begin fetching/executing
    from the reset vector.  The BSP waits for all APs to also
    reach InitReset, where they enter an endless loop.  The BSP
    sends a command to them to execute a HLT instruction and the
    BSP eventually returns from InitReset.  The goal would be to
    preserve this process but prevent APs from rerunning early
    code.

Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>

4 files changed, 105 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
new file mode 100644
index 0000000000..86cc77194c
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -0,0 +1,8 @@
+config SOC_AMD_COMMON_BLOCK_CAR
+	bool
+	default n
+	help
+	  This option allows the SOC to use a standard AMD cache-as-ram (CAR)
+	  implementation.  CAR setup is built into bootblock and teardown in
+	  romstage.  If it is not used the system must implement these functions
+	  separately.
diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc
new file mode 100644
index 0000000000..8e6972ed0a
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/Makefile.inc
@@ -0,0 +1,2 @@
+bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/cache_as_ram.S
+romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
new file mode 100644
index 0000000000..402da3acb6
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/******************************************************************************
+ * $Workfile:: cache_as_ram.S
+ *
+ * Description: CAR setup called from bootblock_crt0.S.
+ *
+ ******************************************************************************
+ */
+
+#include "gcccar.inc"
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+/*
+ * on entry:
+ *   mm0: BIST (ignored)
+ *   mm2_mm1: timestamp at bootblock_protected_mode_entry
+ */
+
+.global bootblock_pre_c_entry
+bootblock_pre_c_entry:
+
+	post_code(0xa0)
+
+	AMD_ENABLE_STACK
+
+	/* Align the stack and keep aligned for call to bootblock_c_entry() */
+	and	$0xfffffff0, %esp
+	sub	$8, %esp
+
+	movd	%mm2, %eax
+	pushl	%eax		/* tsc[63:32] */
+	movd	%mm1, %eax
+	pushl	%eax		/* tsc[31:0] */
+
+before_carstage:
+	post_code(0xa2)
+
+	call	bootblock_c_entry
+	/* Never reached */
+
+.halt_forever:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.halt_forever
diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S
new file mode 100644
index 0000000000..ac36cb0e4f
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/car/exit_car.S
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <gcccar.inc>
+#include <cpu/x86/cache.h>
+
+.code32
+.globl chipset_teardown_car
+
+chipset_teardown_car:
+
+	/* Disable cache */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	AMD_DISABLE_STACK
+
+	/* enable cache */
+	movl	%cr0, %eax
+	andl	$(~(CR0_CD | CR0_NW)), %eax
+	movl	%eax, %cr0
+
+	ret