soc/amd/cezanne,common: factor out CPPC code to common AMD SoC code

The Cezanne CPPC ACPI table generation code also applies to Sabrina, so
move it to the common AMD SoC code directory so that it can be used for
Sabrina too.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ce082a27429948f8af7f55944a1062ba03155da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66400
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

4 files changed, 76 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig
index b4dcec7f38..9c15f21765 100644
--- a/src/soc/amd/common/block/acpi/Kconfig
+++ b/src/soc/amd/common/block/acpi/Kconfig
@@ -8,6 +8,9 @@ config SOC_AMD_COMMON_BLOCK_ACPI
 config SOC_AMD_COMMON_BLOCK_ACPI_ALIB
 	bool
 
+config SOC_AMD_COMMON_BLOCK_ACPI_CPPC
+	bool
+
 config SOC_AMD_COMMON_BLOCK_ACPI_GPIO
 	bool
 
diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc
index 862cf6de3b..f7dc107955 100644
--- a/src/soc/amd/common/block/acpi/Makefile.inc
+++ b/src/soc/amd/common/block/acpi/Makefile.inc
@@ -11,6 +11,7 @@ ramstage-y += pm_state.c
 ramstage-y += tables.c
 ramstage-$(CONFIG_ACPI_BERT) += bert.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_ALIB) += alib.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPPC) += cppc.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO) += gpio.c
 ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_IVRS) += ivrs.c
 
diff --git a/src/soc/amd/common/block/acpi/cppc.c b/src/soc/amd/common/block/acpi/cppc.c
new file mode 100644
index 0000000000..224034d159
--- /dev/null
+++ b/src/soc/amd/common/block/acpi/cppc.c
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_pm.h>
+#include <acpi/acpigen.h>
+#include <amdblocks/cppc.h>
+#include <arch/cpu.h>
+#include <soc/msr.h>
+
+/*
+ * version 2 is expected to be the typical use case.
+ * For now this function 'punts' on version 3 and just
+ * populates the additional fields with 'unsupported'.
+ */
+static void cpu_init_cppc_config(struct cppc_config *config, u32 version)
+{
+	config->version = version;
+
+	config->entries[CPPC_HIGHEST_PERF]		= CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8);
+	config->entries[CPPC_NOMINAL_PERF]		= CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8);
+	config->entries[CPPC_LOWEST_NONL_PERF]		= CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8);
+	config->entries[CPPC_LOWEST_PERF]		= CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8);
+	config->entries[CPPC_GUARANTEED_PERF]		= CPPC_UNSUPPORTED;
+	config->entries[CPPC_DESIRED_PERF]		= CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8);
+	config->entries[CPPC_MIN_PERF]			= CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8);
+	config->entries[CPPC_MAX_PERF]			= CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8);
+	config->entries[CPPC_PERF_REDUCE_TOLERANCE]	= CPPC_UNSUPPORTED;
+	config->entries[CPPC_TIME_WINDOW]		= CPPC_UNSUPPORTED;
+	config->entries[CPPC_COUNTER_WRAP]		= CPPC_UNSUPPORTED;
+	config->entries[CPPC_REF_PERF_COUNTER]		= CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
+	config->entries[CPPC_DELIVERED_PERF_COUNTER]	= CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64);
+	config->entries[CPPC_PERF_LIMITED]		= CPPC_REG_MSR(MSR_CPPC_STATUS, 1, 1);
+	config->entries[CPPC_ENABLE]			= CPPC_REG_MSR(MSR_CPPC_ENABLE, 0, 1);
+
+	if (version < 2)
+		return;
+
+	config->entries[CPPC_AUTO_SELECT]		= CPPC_UNSUPPORTED;
+	config->entries[CPPC_AUTO_ACTIVITY_WINDOW]	= CPPC_UNSUPPORTED;
+	config->entries[CPPC_PERF_PREF]			= CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8);
+	config->entries[CPPC_REF_PERF]			= CPPC_UNSUPPORTED;
+
+	if (version < 3)
+		return;
+
+	config->entries[CPPC_LOWEST_FREQ]		= CPPC_UNSUPPORTED;
+	config->entries[CPPC_NOMINAL_FREQ]		= CPPC_UNSUPPORTED;
+}
+
+void generate_cppc_entries(unsigned int core_id)
+{
+	/* Generate GCPC package in first logical core */
+	if (core_id == 0) {
+		struct cppc_config cppc_config;
+		cpu_init_cppc_config(&cppc_config, CPPC_VERSION_3);
+		acpigen_write_CPPC_package(&cppc_config);
+	}
+
+	/* Write _CPC entry for each logical core */
+	acpigen_write_CPPC_method();
+}
diff --git a/src/soc/amd/common/block/include/amdblocks/cppc.h b/src/soc/amd/common/block/include/amdblocks/cppc.h
new file mode 100644
index 0000000000..7961f60794
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/cppc.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_CPPC_H
+#define AMD_CEZANNE_CPPC_H
+
+#include <types.h>
+#include <acpi/acpigen.h>
+
+struct cppc_config;
+void generate_cppc_entries(unsigned int core_id);
+
+#endif /* AMD_CEZANNE_CPPC_H */