diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-07-16 13:53:29 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-07-19 14:58:53 +0000 |
| commit | 73193cf7b77592d52bb0c60da887af227ac0ace7 (patch) | |
| tree | d0cf340da2b0f165dc80fc3fd0faad2ecf52e51d /src/soc/amd/common/block | |
| parent | f72568cad31092df5c3bc7a87536b84ab178cfa7 (diff) | |
soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHE
This change allows preloading the payload.
BUG=b:179699789
TEST=Boot guybrush and see payload read/decompress drop by 20 ms. We
now spend 7ms decompression from RAM. By switching to LZ4 we drop that
to 500us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/common/block')
| -rw-r--r-- | src/soc/amd/common/block/cpu/Kconfig | 10 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld | 10 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 79e011fadd..11b6c8ccdb 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -24,6 +24,16 @@ config MEMLAYOUT_LD_FILE string default "src/soc/amd/common/block/cpu/noncar/memlayout.ld" +config PAYLOAD_PRELOAD_CACHE_SIZE + hex + default 0x30000 + depends on PAYLOAD_PRELOAD + help + This config sets the size of the payload_preload_cache memory region. + It is used as the destination for the raw payload. This space is only + populated during non-S3, so it doesn't need to be reserved in the + EARLY_RESERVED_DRAM region. + endif # SOC_AMD_COMMON_BLOCK_NONCAR config SOC_AMD_COMMON_BLOCK_MCA_COMMON diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index e5044e6d43..59631f3ada 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -97,6 +97,16 @@ SECTIONS EARLY_RESERVED_DRAM_END(.) +#if CONFIG(PAYLOAD_PRELOAD) + /* + * This section is outside the early_reserved_dram section. We only read + * the payload on non-S3 boots, so we don't need to reserve it from the + * OS. The 64 byte alignment is required by the SPI DMA controller. + */ + . = ALIGN(64); + REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, 64) +#endif + RAMSTAGE(CONFIG_RAMBASE, 8M) } |