diff options
| author | Jon Murphy <jpmurphy@google.com> | 2022-08-05 15:43:44 -0600 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-11 19:15:30 +0000 |
| commit | 4f732420526fdc1c969e910daca573dca72d7b82 (patch) | |
| tree | 26c74fa55c89edbdd7c36be5b966401910437694 /src/soc/amd/common/block | |
| parent | 251e26683e25fdbef329e9e731319ef95b0f7327 (diff) | |
treewide: Rename Sabrina to Mendocino
'Mendocino' was an embargoed name and could previously not be used
in references to Skyrim. coreboot has references to sabrina both
in directory structure and in files. This will make life difficult
for people looking for Mendocino support in the long term. The code
name should be replaced with "mendocino".
BUG=b:239072117
TEST=Builds
Cq-Depend: chromium:3764023
Cq-Depend: chromium:3763392
Cq-Depend: chrome-internal:4876777
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/common/block')
| -rw-r--r-- | src/soc/amd/common/block/acp/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/psp_efs.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/block/lpc/espi_def.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/amd/common/block/acp/Kconfig b/src/soc/amd/common/block/acp/Kconfig index df17f71057..e776416cf4 100644 --- a/src/soc/amd/common/block/acp/Kconfig +++ b/src/soc/amd/common/block/acp/Kconfig @@ -8,4 +8,4 @@ config SOC_AMD_COMMON_BLOCK_ACP_GEN2 bool help Select this option to perform Audio Co-Processor(ACP) configuration. - Used by the ACP in AMD sabrina (family 17h) and possibly newer CPUs. + Used by the ACP in AMD mendocino (family 17h) and possibly newer CPUs. diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index af44765519..1f93807538 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -16,7 +16,7 @@ #elif CONFIG(SOC_AMD_PICASSO) #define SPI_MODE_FIELD spi_readmode_f17_mod_00_2f #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_00_2f -#elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_SABRINA) +#elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_MENDOCINO) #define SPI_MODE_FIELD spi_readmode_f17_mod_30_3f #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_30_3f #else diff --git a/src/soc/amd/common/block/lpc/espi_def.h b/src/soc/amd/common/block/lpc/espi_def.h index dc398a9fc2..1dacffcf51 100644 --- a/src/soc/amd/common/block/lpc/espi_def.h +++ b/src/soc/amd/common/block/lpc/espi_def.h @@ -25,7 +25,7 @@ #define ESPI_WDG_EN (1 << 0) #define ESPI_GLOBAL_CONTROL_1 0x34 -#define ESPI_ALERT_ENABLE (1 << 20) /* Sabrina and later SoCs */ +#define ESPI_ALERT_ENABLE (1 << 20) /* Mendocino and later SoCs */ #define ESPI_RGCMD_INT_MAP_SHIFT 13 #define ESPI_RGCMD_INT_MAP_MASK (0x1f << ESPI_RGCMD_INT_MAP_SHIFT) #define ESPI_RGCMD_INT(irq) ((irq) << ESPI_RGCMD_INT_MAP_SHIFT) |