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authorFelix Held <felix-coreboot@felixheld.de>2024-01-31 12:17:58 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-02-02 20:40:20 +0000
commit416cc665929e4e66bcab3e395daa031401a61fe8 (patch)
tree33a0ea5ec6151cd1f4b876ca2091ff9d07eb4b07 /src/soc/amd/common/block
parent0b76f02892ba37eceff4340c2ca8c4da3f721f9f (diff)
soc/amd: commonize PCI root IOAPIC initialization
Make the initialization of the IOAPIC(s) in the PCI root(s) common across all AMD family 17h+ SoCs. For this the more general implementation from the Genoa code that supports multiple PC roots is moved to the common AMD code. All other family 17h+ SoCs are then adapted to use the common code. For those non-Genoa SoCs, the initialization of this second IOAPIC is moved from the northbridge device to the domain device above to match Genoa. Test=Both the FCH IOAPIC and the PCIe root IOAPIC are still initialized on Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80286 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/block')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/root_complex.h2
-rw-r--r--src/soc/amd/common/block/root_complex/Makefile.mk7
-rw-r--r--src/soc/amd/common/block/root_complex/ioapic.c17
3 files changed, 25 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/root_complex.h b/src/soc/amd/common/block/include/amdblocks/root_complex.h
index cac659e756..767221ec06 100644
--- a/src/soc/amd/common/block/include/amdblocks/root_complex.h
+++ b/src/soc/amd/common/block/include/amdblocks/root_complex.h
@@ -31,4 +31,6 @@ signed int get_iohc_fabric_id(struct device *domain);
void read_fsp_resources(struct device *dev, unsigned long *idx);
+void amd_pci_domain_init(struct device *domain);
+
#endif /* AMD_BLOCK_ROOT_COMPLEX_H */
diff --git a/src/soc/amd/common/block/root_complex/Makefile.mk b/src/soc/amd/common/block/root_complex/Makefile.mk
index ba550bda6b..07f3ab108e 100644
--- a/src/soc/amd/common/block/root_complex/Makefile.mk
+++ b/src/soc/amd/common/block/root_complex/Makefile.mk
@@ -1,2 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
-ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX) += non_pci_resources.c
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX),y)
+
+ramstage-y += ioapic.c
+ramstage-y += non_pci_resources.c
+
+endif # CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX
diff --git a/src/soc/amd/common/block/root_complex/ioapic.c b/src/soc/amd/common/block/root_complex/ioapic.c
new file mode 100644
index 0000000000..cdeb53239b
--- /dev/null
+++ b/src/soc/amd/common/block/root_complex/ioapic.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/ioapic.h>
+#include <amdblocks/root_complex.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <device/resource.h>
+#include <types.h>
+
+void amd_pci_domain_init(struct device *domain)
+{
+ struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
+ if (!res)
+ return;
+
+ register_new_ioapic((void *)(uintptr_t)res->base);
+}