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authorFelix Held <felix-coreboot@felixheld.de>2021-06-11 02:11:22 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-02-13 19:23:26 +0000
commit399d3cf8782673bb1cf62bca028d43eb95cc5f6e (patch)
tree8854019f0b2525e4329324d22e862e17369bfca9 /src/soc/amd/common/block
parent0e688b113d7fd98dfdb69cd0a407c8efcd968456 (diff)
soc/amd/common/include/ioapic: make IOAPIC IDs not depend on MAX_CPUS
Since the APIC bus isn't used since a long time and the IOAPIC and LAPIC talk to each other via the system bus, there is no longer the requirement that the IOAPIC IDs mustn't overlap with the LAPIC IDs that start at 0 and end at CONFIG_MAX_CPUS - 1. The current Intel code uses 2 as the IOAPIC ID while most of their CPUs have more than 2 logical cores resulting in the IOAPIC having the same ID as one of the LAPICs. All chipsets in soc/amd use the defines for FCH_IOAPIC_ID and GNB_IOAPIC_ID for initializing the IOAPIC register, writing both MADT and IVRS ACPI tables and there's no MPTable support for those SoCs that might also rely on those IDs being consistent. This patch changes the definitions for FCH_IOAPIC_ID and GNB_IOAPIC_ID from CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 to 0 and 1. This also makes sure that the IOAPIC IDs still fit in 4 bits despite Cezanne having a CONFIG_MAX_CPUS of 16 resulting in the IOAPIC IDs being larger than 4 bits with the old code. While the Cezanne FCH IOAPIC supports 8 bits of IOAPIC IDs, this is non-standard. TEST=AMD Mandolin and Google Liara still work. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Id3a356480bb8407e0347cb5cef691fde7edc8deb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/amd/common/block')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/ioapic.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/ioapic.h b/src/soc/amd/common/block/include/amdblocks/ioapic.h
index 4c10a84a03..bd1c363242 100644
--- a/src/soc/amd/common/block/include/amdblocks/ioapic.h
+++ b/src/soc/amd/common/block/include/amdblocks/ioapic.h
@@ -3,7 +3,8 @@
#ifndef AMD_BLOCK_IOAPIC_H
#define AMD_BLOCK_IOAPIC_H
-#define FCH_IOAPIC_ID CONFIG_MAX_CPUS
-#define GNB_IOAPIC_ID (CONFIG_MAX_CPUS + 1)
+/* Since the old APIC bus isn't used any more, the IOAPIC IDs can be < CONFIG_MAX_CPUS */
+#define FCH_IOAPIC_ID 0
+#define GNB_IOAPIC_ID 1
#endif /* AMD_BLOCK_IOAPIC_H */