diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-08-03 00:29:55 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-08 19:41:51 +0000 |
| commit | 382c83e6db6a390624ff5ac067ff4480b2c06e73 (patch) | |
| tree | d8f4f148b24c96b9a9f804bfb3d0352f2ba3ea13 /src/soc/amd/common/block | |
| parent | 4078d14a7eb0ccd83ed576e0b4b11e0af5893671 (diff) | |
soc/amd/*/include/data_fabric: rename D18F0_MMIO_* to DF_MMIO_*
Now that the data fabric PCI device functions are included in the
register definitions, the remaining data fabric device function numbers
can be dropped from the define names.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia0355838ac1d513ba562fd6fb4672342dd383498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76888
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/common/block')
| -rw-r--r-- | src/soc/amd/common/block/data_fabric/data_fabric_helper.c | 10 | ||||
| -rw-r--r-- | src/soc/amd/common/block/data_fabric/domain.c | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/data_fabric.h | 6 |
3 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index 812e0d442c..e19b278cc0 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -57,11 +57,11 @@ void data_fabric_print_mmio_conf(void) /* Base and limit address registers don't contain the lower address bits, but are shifted by D18F0_MMIO_SHIFT bits */ base = (uint64_t)data_fabric_broadcast_read32(DF_MMIO_BASE(i)) - << D18F0_MMIO_SHIFT; + << DF_MMIO_SHIFT; limit = (uint64_t)data_fabric_broadcast_read32(DF_MMIO_LIMIT(i)) - << D18F0_MMIO_SHIFT; + << DF_MMIO_SHIFT; /* Lower D18F0_MMIO_SHIFT address limit bits are all 1 */ - limit += (1 << D18F0_MMIO_SHIFT) - 1; + limit += (1 << DF_MMIO_SHIFT) - 1; printk(BIOS_SPEW, " %2u %16llx %16llx %8x %s %s %s %4x\n", i, base, limit, control.raw, control.re ? "x" : " ", @@ -121,8 +121,8 @@ void data_fabric_set_mmio_np(void) int reg; uint32_t base, limit; union df_mmio_control ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; + const uint32_t np_bot = HPET_BASE_ADDRESS >> DF_MMIO_SHIFT; + const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> DF_MMIO_SHIFT; data_fabric_print_mmio_conf(); diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index f28bb1228f..9f0f48c325 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -41,8 +41,8 @@ static void data_fabric_get_mmio_base_size(unsigned int reg, const uint32_t base_reg = data_fabric_broadcast_read32(DF_MMIO_BASE(reg)); const uint32_t limit_reg = data_fabric_broadcast_read32(DF_MMIO_LIMIT(reg)); /* The raw register values are bits 47..16 of the actual address */ - *mmio_base = (resource_t)base_reg << D18F0_MMIO_SHIFT; - *mmio_limit = (((resource_t)limit_reg + 1) << D18F0_MMIO_SHIFT) - 1; + *mmio_base = (resource_t)base_reg << DF_MMIO_SHIFT; + *mmio_limit = (((resource_t)limit_reg + 1) << DF_MMIO_SHIFT) - 1; } static void print_df_mmio_outside_of_cpu_mmio_error(unsigned int reg) diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index ad1f97bafb..911b504cb6 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -18,9 +18,9 @@ #define DF_MMIO_REG_OFFSET(instance) ((instance) * DF_MMIO_REG_SET_SIZE * sizeof(uint32_t)) /* The number of data fabric MMIO registers is SoC-specific */ -#define DF_MMIO_BASE(reg) (D18F0_MMIO_BASE0 + DF_MMIO_REG_OFFSET(reg)) -#define DF_MMIO_LIMIT(reg) (D18F0_MMIO_LIMIT0 + DF_MMIO_REG_OFFSET(reg)) -#define DF_MMIO_CONTROL(reg) (D18F0_MMIO_CTRL0 + DF_MMIO_REG_OFFSET(reg)) +#define DF_MMIO_BASE(reg) (DF_MMIO_BASE0 + DF_MMIO_REG_OFFSET(reg)) +#define DF_MMIO_LIMIT(reg) (DF_MMIO_LIMIT0 + DF_MMIO_REG_OFFSET(reg)) +#define DF_MMIO_CONTROL(reg) (DF_MMIO_CTRL0 + DF_MMIO_REG_OFFSET(reg)) /* Last 12GB of the usable address space are reserved */ #define DF_RESERVED_TOP_12GB_MMIO_SIZE (12ULL * GiB) |