soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common

The data_fabric_set_mmio_np function is effectively identical, so move
it to common code.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

2 files changed, 89 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c
index 0fcee3642b..f1a067f4e0 100644
--- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c
+++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c
@@ -2,7 +2,9 @@
 
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/pci_devs.h>
+#include <arch/hpet.h>
 #include <console/console.h>
+#include <cpu/x86/lapic_def.h>
 #include <device/pci_ops.h>
 #include <soc/data_fabric.h>
 #include <soc/pci_devs.h>
@@ -82,3 +84,89 @@ int data_fabric_find_unused_mmio_reg(void)
 	}
 	return -1;
 }
+
+void data_fabric_set_mmio_np(void)
+{
+	/*
+	 * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP.
+	 *
+	 * AGESA has already programmed the NB MMIO routing, however nothing
+	 * is yet marked as non-posted.
+	 *
+	 * If there exists an overlapping routing base/limit pair, trim its
+	 * base or limit to avoid the new NP region.  If any pair exists
+	 * completely within HPET-LAPIC range, remove it.  If any pair surrounds
+	 * HPET-LAPIC, it must be split into two regions.
+	 *
+	 * TODO(b/156296146): Remove the settings from AGESA and allow coreboot
+	 * to own everything.  If not practical, consider erasing all settings
+	 * and have coreboot reprogram them.  At that time, make the source
+	 * below more flexible.
+	 *   * Note that the code relies on the granularity of the HPET and
+	 *     LAPIC addresses being sufficiently large that the shifted limits
+	 *     +/-1 are always equivalent to the non-shifted values +/-1.
+	 */
+
+	unsigned int i;
+	int reg;
+	uint32_t base, limit, ctrl;
+	const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT;
+	const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT;
+
+	data_fabric_print_mmio_conf();
+
+	for (i = 0; i < NUM_NB_MMIO_REGS; i++) {
+		/* Adjust all registers that overlap */
+		ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i));
+		if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE)))
+			continue; /* not enabled */
+
+		base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i));
+		limit = data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i));
+
+		if (base > np_top || limit < np_bot)
+			continue; /* no overlap at all */
+
+		if (base >= np_bot && limit <= np_top) {
+			data_fabric_disable_mmio_reg(i); /* 100% within, so remove */
+			continue;
+		}
+
+		if (base < np_bot && limit > np_top) {
+			/* Split the configured region */
+			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
+			reg = data_fabric_find_unused_mmio_reg();
+			if (reg < 0) {
+				/* Although a pair could be freed later, this condition is
+				 * very unusual and deserves analysis.  Flag an error and
+				 * leave the topmost part unconfigured. */
+				printk(BIOS_ERR, "Not enough NB MMIO routing registers\n");
+				continue;
+			}
+			data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1);
+			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit);
+			data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl);
+			continue;
+		}
+
+		/* If still here, adjust only the base or limit */
+		if (base <= np_bot)
+			data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(i), np_bot - 1);
+		else
+			data_fabric_broadcast_write32(0, NB_MMIO_BASE(i), np_top + 1);
+	}
+
+	reg = data_fabric_find_unused_mmio_reg();
+	if (reg < 0) {
+		printk(BIOS_ERR, "cannot configure region as NP\n");
+		return;
+	}
+
+	data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot);
+	data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top);
+	data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg),
+			   (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP
+				   | DF_MMIO_WE | DF_MMIO_RE);
+
+	data_fabric_print_mmio_conf();
+}
diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h
index 604c24e16f..5cc7f4867b 100644
--- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h
+++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h
@@ -45,5 +45,6 @@ void data_fabric_broadcast_write32(uint8_t function, uint16_t reg, uint32_t data
 void data_fabric_print_mmio_conf(void);
 void data_fabric_disable_mmio_reg(unsigned int reg);
 int data_fabric_find_unused_mmio_reg(void);
+void data_fabric_set_mmio_np(void);
 
 #endif /* AMD_BLOCK_DATA_FABRIC_H */