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| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-09 11:19:29 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-10 19:00:34 +0000 |
| commit | 6ba1fcac3402a8719b6d080eb78e67b059a9b2ad (patch) | |
| tree | c2b4f8d899afa378e521c64c8aae4af157eb7d59 /src/soc/amd/common/block/spi/fch_spi.c | |
| parent | 4f1147b54124609284e390b9a1176a90877848f5 (diff) | |
soc/amd/cezanne: Add SPI registers
These are identical to picasso.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ef4c51ef6d656b3b035d97a56b1875b40e89210
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/common/block/spi/fch_spi.c')
0 files changed, 0 insertions, 0 deletions