soc/amd/common/block/spi: Add support for common SPI configuration

This change adds support for following SPI configuration functions to
common block SPI driver and exposes them to be used by SoC:
1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM,
enables prefetching, disables 4dw burst mode and sets SPI speed and mode.
2. fch_spi_config_modes(): This allows SoC to configure SPI speed and
mode. It uses SPI settings from soc_amd_common_config to configure the
speed and mode.

These functions expect SoC to include soc_amd_common_config in SoC
chip config and mainboard to configure these settings in device tree.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41248
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 86 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c
new file mode 100644
index 0000000000..950eee2947
--- /dev/null
+++ b/src/soc/amd/common/block/spi/fch_spi.c
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <amdblocks/chip.h>
+#include <amdblocks/lpc.h>
+#include <amdblocks/spi.h>
+#include <arch/mmio.h>
+#include <console/console.h>
+#include <soc/iomap.h>
+#include <stdint.h>
+
+static uintptr_t fch_spi_base(void)
+{
+	uintptr_t base;
+
+	base = lpc_get_spibase();
+
+	if (base)
+		return base;
+
+	lpc_set_spibase(SPI_BASE_ADDRESS);
+	lpc_enable_spi_rom(SPI_ROM_ENABLE);
+
+	return SPI_BASE_ADDRESS;
+}
+
+static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm)
+{
+	uintptr_t base = fch_spi_base();
+
+	write16((void *)(base + SPI100_SPEED_CONFIG), SPI_SPEED_CFG(norm, fast, alt, tpm));
+	write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100);
+}
+
+static void fch_spi_disable_4dw_burst(void)
+{
+	uintptr_t base = fch_spi_base();
+	uint16_t val = read16((void *)(base + SPI100_HOST_PREF_CONFIG));
+
+	write16((void *)(base + SPI100_HOST_PREF_CONFIG), val & ~SPI_RD4DW_EN_HOST);
+}
+
+static void fch_spi_set_read_mode(u32 mode)
+{
+	uintptr_t base = fch_spi_base();
+	uint32_t val = read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK;
+
+	write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode));
+}
+
+static void fch_spi_config_mb_modes(void)
+{
+	const struct soc_amd_common_config *cfg = soc_get_common_config();
+
+	if (!cfg)
+		die("Common config structure is NULL!\n");
+
+	const struct spi_config *spi_cfg = &cfg->spi_config;
+
+	fch_spi_set_read_mode(spi_cfg->read_mode);
+	fch_spi_set_spi100(spi_cfg->normal_speed, spi_cfg->fast_speed,
+			   spi_cfg->altio_speed, spi_cfg->tpm_speed);
+}
+
+static void fch_spi_config_em100_modes(void)
+{
+	fch_spi_set_read_mode(SPI_READ_MODE_NORMAL33M);
+	fch_spi_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M);
+}
+
+void fch_spi_config_modes(void)
+{
+	if (CONFIG(EM100))
+		fch_spi_config_em100_modes();
+	else
+		fch_spi_config_mb_modes();
+}
+
+void fch_spi_early_init(void)
+{
+	lpc_set_spibase(SPI_BASE_ADDRESS);
+	lpc_enable_spi_rom(SPI_ROM_ENABLE);
+	lpc_enable_spi_prefetch();
+	fch_spi_disable_4dw_burst();
+	fch_spi_config_modes();
+}