soc/amd/common/block: Create new SPI code

Create a new SPI code that overrides flash operations and uses the SPI
controller within the FCH to its fullest.

Reference: Family 15h models 70h-7Fh BKDG revision 3.06 (public)

BUG=b:136595978
TEST=Build and boot grunt using this code, with debug enabled. Check
output.

Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

1 files changed, 30 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc
new file mode 100644
index 0000000000..b94eda405a
--- /dev/null
+++ b/src/soc/amd/common/block/spi/Makefile.inc
@@ -0,0 +1,30 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SPI),y)
+
+bootblock-y += fch_spi_ctrl.c
+bootblock-y += fch_spi_flash.c
+bootblock-y += fch_spi_special.c
+bootblock-y += fch_spi_table.c
+romstage-y += fch_spi_ctrl.c
+romstage-y += fch_spi_flash.c
+romstage-y += fch_spi_special.c
+romstage-y += fch_spi_table.c
+verstage-y += fch_spi_ctrl.c
+verstage-y += fch_spi_flash.c
+verstage-y += fch_spi_special.c
+verstage-y += fch_spi_table.c
+postcar-y += fch_spi_ctrl.c
+postcar-y += fch_spi_flash.c
+postcar-y += fch_spi_special.c
+postcar-y += fch_spi_table.c
+ramstage-y += fch_spi_ctrl.c
+ramstage-y += fch_spi_flash.c
+ramstage-y += fch_spi_special.c
+ramstage-y += fch_spi_table.c
+ifeq ($(CONFIG_SPI_FLASH_SMM),y)
+smm-y += fch_spi_ctrl.c
+smm-y += fch_spi_flash.c
+smm-y += fch_spi_special.c
+smm-y += fch_spi_table.c
+endif
+
+endif