diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-10-12 16:04:08 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-08 21:58:59 +0000 |
| commit | 596ecec009d722aebbfc16074b89bc78dc9ede26 (patch) | |
| tree | d9722ff5cb487f65e7eb91c27cb237deed33295c /src/soc/amd/common/block/psp/Kconfig | |
| parent | 154239aff1602e0ae27f9ce1f2df0647e4aef0a8 (diff) | |
soc/amd/common/psp: Add command to load fw blobs
An upcoming PSP firmware change will allow coreboot to load the two
SMU firmware blobs (one runs in SRAM and the other in DRAM). The
traditional method is for the PSP to control most of the process,
e.g. loading the SRAM version prior to releasing the x86 reset.
Add a new command that can instruct the PSP to load a firmware blob
from a location in the flash.
The definition for commands 19 and 1a differ from others in that they
do not use a command/response buffer. Instead, the PSP will look in
the command/response pointer registers directly for the blob's
address.
BUG=b:66339938
Change-Id: I8431af341930f45ac74f471628b4dc4ede7735f4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/amd/common/block/psp/Kconfig')
| -rw-r--r-- | src/soc/amd/common/block/psp/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 69958f21aa..0517a2f33f 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -4,3 +4,15 @@ config SOC_AMD_COMMON_BLOCK_PSP help This option builds in the Platform Security Processor initialization functions. + +config SOC_AMD_PSP_SELECTABLE_SMU_FW + bool + default n + help + Some PSP implementations allow storing SMU firmware into cbfs and + calling the PSP to load the blobs at the proper time. + + The soc/<codename> should select this if its PSP supports the feature + and each mainboard can choose to select an appropriate fanless or + fanned set of blobs. Ask your AMD representative whether your APU + is considered fanless. |