soc/amd/common/lpc: Add decode disable function

It is already trivial to set D14F3x44 to 0, but add a function to wipe
both that and the settings in D14F3x48, along with x48's associated
addresses.

Change-Id: Ibec25562b2a1568681aea7caf86f00094c436a50
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

1 files changed, 19 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 008d14c34e..1d46acbf5c 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -170,6 +170,25 @@ void lpc_enable_decode(uint32_t decodes)
 	pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes);
 }
 
+/*
+ * Clear all decoding to the LPC bus and erase any range registers associated
+ * with the enable bits.
+ */
+void lpc_disable_decodes(void)
+{
+	uint32_t reg;
+
+	lpc_enable_decode(0);
+	reg = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
+	reg &= LPC_SYNC_TIMEOUT_COUNT_MASK | LPC_SYNC_TIMEOUT_COUNT_ENABLE;
+	pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg);
+
+	/* D14F3x48 enables ranges configured in additional registers */
+	pci_write_config32(_LPCB_DEV, LPC_MEM_PORT1, 0);
+	pci_write_config32(_LPCB_DEV, LPC_MEM_PORT0, 0);
+	pci_write_config32(_LPCB_DEV, LPC_WIDEIO2_GENERIC_PORT, 0);
+}
+
 uintptr_t lpc_spibase(void)
 {
 	u32 base, enables;