soc/amd/common: factor out SMU code from Picasso

The SMU mailbox access code from Picasso can be reused in the next
generation, so factor out the code to soc/amd/common/block/smu. Since
the mailbox register offsets in the indirect address space, the number
of arguments and the message IDs don't always match between different
devices, keep those in the soc-specific directories.

Change-Id: Ibaf5b91ab35428e4c771e7163c6e0c4fc50371e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

1 files changed, 26 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/include/amdblocks/smu.h b/src/soc/amd/common/block/include/amdblocks/smu.h
new file mode 100644
index 0000000000..57ef3b324e
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/smu.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __AMD_BLOCK_SMU_H__
+#define __AMD_BLOCK_SMU_H__
+
+#include <types.h>
+#include <soc/smu.h> /* SoC-dependent definitions for SMU access */
+
+/* SMU registers accessed indirectly using an index/data pair in D0F00 config space */
+#define SMU_INDEX_ADDR		0xb8 /* 32 bit */
+#define SMU_DATA_ADDR		0xbc /* 32 bit */
+
+/* Arguments indexed locations are contiguous; the number is SoC-dependent */
+#define REG_ADDR_MESG_ARG(x)	(REG_ADDR_MESG_ARGS_BASE + ((x) * sizeof(uint32_t)))
+
+struct smu_payload {
+	uint32_t msg[SMU_NUM_ARGS];
+};
+
+/*
+ * Send a message and bi-directional payload to the SMU. The SMU's response, if any, is
+ * returned via *arg. Returns CB_SUCCESS if success or CB_ERR on failure.
+ */
+enum cb_err send_smu_message(enum smu_message_id message_id, struct smu_payload *arg);
+
+#endif /* __AMD_BLOCK_SMU_H__ */