soc/amd/common: Access ACPIMMIO via proper symbols

Using proper symbols for base addresses, it is possible to
only define the symbols for base addresses implemented for
the specific platform and executing stage.

Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 118 insertions, 158 deletions

diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 84a9360d1b..3d0cf06688 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -5,86 +5,46 @@
 
 #include <device/mmio.h>
 #include <types.h>
-#include <amdblocks/acpimmio_map.h>
+
+/* IO index/data for accessing PMIO prior to enabling MMIO decode */
+#define PM_INDEX			0xcd6
+#define PM_DATA				0xcd7
 
 /*
- * The following AcpiMmio register block mapping represents definitions
- * that have been documented in AMD publications.  All blocks aren't
- * implemented in all products, so the caller should be careful not to
- * inadvertently access a non-existent block.  The definitions within
- * each block are also subject to change across products.  Please refer
- * to the appropriate RRG, the BKDG, or PPR for the product.
- *
- * The base address is configurable in older products, but defaults to
- * 0xfed80000.  The address is fixed at 0xfed80000 in newer products.
- *
- * +---------------------------------------------------------------------------+
- * |0x000    SMBus PCI space                                                   |
- * |           * Dual-mapped to PCI configuration header of D14F0              |
- * +---------------------------------------------------------------------------+
- * |0x100    GPIO configuration registers                                      |
- * |           * old style, never implemented with newer style                 |
- * +---------------------------------------------------------------------------+
- * |0x200    SMI configuration registers                                       |
- * +---------------------------------------------------------------------------+
- * |0x300    Power Management registers                                        |
- * |           * Dual-mapped via IO Index/Data 0xcd6/0xcd7 (byte access only)  |
- * +---------------------------------------------------------------------------+
- * |0x400    Power Management 2 registers                                      |
- * +---------------------------------------------------------------------------+
- * |0x500    BIOS RAM                                                          |
- * |           * General-purpose storage in S3 domain                          |
- * |           * Byte access only                                              |
- * +---------------------------------------------------------------------------+
- * |0x600    CMOS RAM                                                          |
- * |           * Dual-mapped to storage at Alt RTC Index/Data (0x72/0x73)      |
- * |           * Byte access only                                              |
- * +---------------------------------------------------------------------------+
- * |0x700    CMOS                                                              |
- * |           * Dual-mapped to storage at RTC Index/Data (0x70/0x71)          |
- * |           * Byte access only                                              |
- * +---------------------------------------------------------------------------+
- * |0x800    Standard ACPI registers                                           |
- * |           * Dual-mapped to I/O ACPI registers                             |
- * +---------------------------------------------------------------------------+
- * |0x900    ASF controller registers                                          |
- * |           * Dual-mapped to I/O ASF controller registers                   |
- * +---------------------------------------------------------------------------+
- * |0xa00    SMBus controller registers                                        |
- * |           * Dual-mapped to I/O SMBus controller registers                 |
- * +---------------------------------------------------------------------------+
- * |0xb00    WDT registers                                                     |
- * |           * Dual-mapped to WDT registers, typ. enabled at 0xfeb00000      |
- * +---------------------------------------------------------------------------+
- * |0xc00    HPET registers                                                    |
- * |           * Dual-mapped to HPET registers, typ. enabled at 0xfed00000     |
- * +---------------------------------------------------------------------------+
- * |0xd00    MUX configuration registers for GPIO signals                      |
- * +---------------------------------------------------------------------------+
- * |0xe00    Miscellaneous registers                                           |
- * +---------------------------------------------------------------------------+
- * |0x1000   Serial debug bus                                                  |
- * +---------------------------------------------------------------------------+
- * |0x1400   DP-VGA                                                            |
- * +---------------------------------------------------------------------------+
- * |0x1500   GPIO configuration registers bank 0                               |
- * |           * new style, never implemented with older style                 |
- * +---------------------------------------------------------------------------+
- * |0x1600   GPIO configuration registers bank 1                               |
- * |           * new style, never implemented with older style                 |
- * +---------------------------------------------------------------------------+
- * |0x1700   GPIO configuration registers bank 2                               |
- * |           * new style, never implemented with older style                 |
- * +---------------------------------------------------------------------------+
- * |0x1c00   xHCI Power Management registers                                   |
- * +---------------------------------------------------------------------------+
- * |0x1d00   Wake device (AC DC timer)                                         |
- * +---------------------------------------------------------------------------+
- * |0x1e00   Always On Always Connect registers                                |
- * +---------------------------------------------------------------------------+
+ * Earlier devices enable the ACPIMMIO bank decodes in PMx24. All discrete FCHs
+ * and the Kabini SoC fall into this category. Kabini's successor, Mullins, uses
+ * this newer method of enable in PMx04.
  */
 
-/* Enable the AcpiMmio range at 0xfed80000 */
+#define ACPIMMIO_DECODE_REGISTER_24 0x24
+#define   PM_24_ACPIMMIO_DECODE_EN	BIT(0)
+
+#define ACPIMMIO_DECODE_REGISTER_04 0x4
+#define   PM_04_BIOSRAM_DECODE_EN	BIT(0)
+#define   PM_04_ACPIMMIO_DECODE_EN	BIT(1)
+
+extern uint8_t *const acpimmio_gpio_100;
+extern uint8_t *const acpimmio_sm_pci;
+extern uint8_t *const acpimmio_smi;
+extern uint8_t *const acpimmio_pmio;
+extern uint8_t *const acpimmio_pmio2;
+extern uint8_t *const acpimmio_biosram;
+extern uint8_t *const acpimmio_cmosram;
+extern uint8_t *const acpimmio_cmos;
+extern uint8_t *const acpimmio_acpi;
+extern uint8_t *const acpimmio_asf;
+extern uint8_t *const acpimmio_smbus;
+extern uint8_t *const acpimmio_wdt;
+extern uint8_t *const acpimmio_hpet;
+extern uint8_t *const acpimmio_iomux;
+extern uint8_t *const acpimmio_misc;
+extern uint8_t *const acpimmio_dpvga;
+extern uint8_t *const acpimmio_gpio0;
+extern uint8_t *const acpimmio_gpio1;
+extern uint8_t *const acpimmio_gpio2;
+extern uint8_t *const acpimmio_xhci_pm;
+extern uint8_t *const acpimmio_acdc_tmr;
+extern uint8_t *const acpimmio_aoac;
 
 /* For older discrete FCHs */
 void enable_acpimmio_decode_pm24(void);
@@ -102,417 +62,417 @@ void pm_io_write32(uint8_t reg, uint32_t value);
 
 static inline uint8_t sm_pci_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg));
+	return read8(acpimmio_sm_pci + reg);
 }
 
 static inline uint16_t sm_pci_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg));
+	return read16(acpimmio_sm_pci + reg);
 }
 
 static inline uint32_t sm_pci_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg));
+	return read32(acpimmio_sm_pci + reg);
 }
 
 static inline void sm_pci_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value);
+	write8(acpimmio_sm_pci + reg, value);
 }
 
 static inline void sm_pci_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value);
+	write16(acpimmio_sm_pci + reg, value);
 }
 
 static inline void sm_pci_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value);
+	write32(acpimmio_sm_pci + reg, value);
 }
 
 static inline uint8_t smi_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_SMI_BASE + reg));
+	return read8(acpimmio_smi + reg);
 }
 
 static inline uint16_t smi_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_SMI_BASE + reg));
+	return read16(acpimmio_smi + reg);
 }
 
 static inline uint32_t smi_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_SMI_BASE + reg));
+	return read32(acpimmio_smi + reg);
 }
 
 static inline void smi_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_SMI_BASE + reg), value);
+	write8(acpimmio_smi + reg, value);
 }
 
 static inline void smi_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_SMI_BASE + reg), value);
+	write16(acpimmio_smi + reg, value);
 }
 
 static inline void smi_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_SMI_BASE + reg), value);
+	write32(acpimmio_smi + reg, value);
 }
 
 static inline uint8_t pm_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_PMIO_BASE + reg));
+	return read8(acpimmio_pmio + reg);
 }
 
 static inline uint16_t pm_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_PMIO_BASE + reg));
+	return read16(acpimmio_pmio + reg);
 }
 
 static inline uint32_t pm_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_PMIO_BASE + reg));
+	return read32(acpimmio_pmio + reg);
 }
 
 static inline void pm_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_PMIO_BASE + reg), value);
+	write8(acpimmio_pmio + reg, value);
 }
 
 static inline void pm_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_PMIO_BASE + reg), value);
+	write16(acpimmio_pmio + reg, value);
 }
 
 static inline void pm_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_PMIO_BASE + reg), value);
+	write32(acpimmio_pmio + reg, value);
 }
 
 static inline uint8_t pm2_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_PMIO2_BASE + reg));
+	return read8(acpimmio_pmio2 + reg);
 }
 
 static inline uint16_t pm2_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_PMIO2_BASE + reg));
+	return read16(acpimmio_pmio2 + reg);
 }
 
 static inline uint32_t pm2_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_PMIO2_BASE + reg));
+	return read32(acpimmio_pmio2 + reg);
 }
 
 static inline void pm2_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_PMIO2_BASE + reg), value);
+	write8(acpimmio_pmio2 + reg, value);
 }
 
 static inline void pm2_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_PMIO2_BASE + reg), value);
+	write16(acpimmio_pmio2 + reg, value);
 }
 
 static inline void pm2_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_PMIO2_BASE + reg), value);
+	write32(acpimmio_pmio2 + reg, value);
 }
 
 static inline uint8_t acpi_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_ACPI_BASE + reg));
+	return read8(acpimmio_acpi + reg);
 }
 
 static inline uint16_t acpi_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_ACPI_BASE + reg));
+	return read16(acpimmio_acpi + reg);
 }
 
 static inline uint32_t acpi_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_ACPI_BASE + reg));
+	return read32(acpimmio_acpi + reg);
 }
 
 static inline void acpi_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_ACPI_BASE + reg), value);
+	write8(acpimmio_acpi + reg, value);
 }
 
 static inline void acpi_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_ACPI_BASE + reg), value);
+	write16(acpimmio_acpi + reg, value);
 }
 
 static inline void acpi_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_ACPI_BASE + reg), value);
+	write32(acpimmio_acpi + reg, value);
 }
 
 static inline uint8_t asf_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_ASF_BASE + reg));
+	return read8(acpimmio_asf + reg);
 }
 
 static inline uint16_t asf_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_ASF_BASE + reg));
+	return read16(acpimmio_asf + reg);
 }
 
 static inline void asf_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_ASF_BASE + reg), value);
+	write8(acpimmio_asf + reg, value);
 }
 
 static inline void asf_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_ASF_BASE + reg), value);
+	write16(acpimmio_asf + reg, value);
 }
 
 static inline uint8_t smbus_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_SMBUS_BASE + reg));
+	return read8(acpimmio_smbus + reg);
 }
 
 static inline uint16_t smbus_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_SMBUS_BASE + reg));
+	return read16(acpimmio_smbus + reg);
 }
 
 static inline void smbus_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value);
+	write8(acpimmio_smbus + reg, value);
 }
 
 static inline void smbus_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value);
+	write16(acpimmio_smbus + reg, value);
 }
 
 static inline uint8_t iomux_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_IOMUX_BASE + reg));
+	return read8(acpimmio_iomux + reg);
 }
 
 static inline uint16_t iomux_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_IOMUX_BASE + reg));
+	return read16(acpimmio_iomux + reg);
 }
 
 static inline uint32_t iomux_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_IOMUX_BASE + reg));
+	return read32(acpimmio_iomux + reg);
 }
 
 static inline void iomux_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
+	write8(acpimmio_iomux + reg, value);
 }
 
 static inline void iomux_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
+	write16(acpimmio_iomux + reg, value);
 }
 
 static inline void iomux_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
+	write32(acpimmio_iomux + reg, value);
 }
 
 static inline uint8_t misc_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_MISC_BASE + reg));
+	return read8(acpimmio_misc + reg);
 }
 
 static inline uint16_t misc_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_MISC_BASE + reg));
+	return read16(acpimmio_misc + reg);
 }
 
 static inline uint32_t misc_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_MISC_BASE + reg));
+	return read32(acpimmio_misc + reg);
 }
 
 static inline void misc_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_MISC_BASE + reg), value);
+	write8(acpimmio_misc + reg, value);
 }
 
 static inline void misc_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_MISC_BASE + reg), value);
+	write16(acpimmio_misc + reg, value);
 }
 
 static inline void misc_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_MISC_BASE + reg), value);
+	write32(acpimmio_misc + reg, value);
 }
 
 /* Old GPIO configuration registers */
 static inline uint8_t gpio_100_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_GPIO_BASE_100 + reg));
+	return read8(acpimmio_gpio_100 + reg);
 }
 
 static inline uint16_t gpio_100_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_GPIO_BASE_100 + reg));
+	return read16(acpimmio_gpio_100 + reg);
 }
 
 static inline uint32_t gpio_100_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_GPIO_BASE_100 + reg));
+	return read32(acpimmio_gpio_100 + reg);
 }
 
 static inline void gpio_100_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value);
+	write8(acpimmio_gpio_100 + reg, value);
 }
 
 static inline void gpio_100_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value);
+	write16(acpimmio_gpio_100 + reg, value);
 }
 
 static inline void gpio_100_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value);
+	write32(acpimmio_gpio_100 + reg, value);
 }
 
 /* New GPIO banks configuration registers */
 /* GPIO bank 0 */
 static inline uint8_t gpio0_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_GPIO0_BASE + reg));
+	return read8(acpimmio_gpio0 + reg);
 }
 
 static inline uint16_t gpio0_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_GPIO0_BASE + reg));
+	return read16(acpimmio_gpio0 + reg);
 }
 
 static inline uint32_t gpio0_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_GPIO0_BASE + reg));
+	return read32(acpimmio_gpio0 + reg);
 }
 
 static inline void gpio0_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_GPIO0_BASE + reg), value);
+	write8(acpimmio_gpio0 + reg, value);
 }
 
 static inline void gpio0_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_GPIO0_BASE + reg), value);
+	write16(acpimmio_gpio0 + reg, value);
 }
 
 static inline void gpio0_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_GPIO0_BASE + reg), value);
+	write32(acpimmio_gpio0 + reg, value);
 }
 
 /* GPIO bank 1 */
 static inline uint8_t gpio1_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_GPIO1_BASE + reg));
+	return read8(acpimmio_gpio1 + reg);
 }
 
 static inline uint16_t gpio1_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_GPIO1_BASE + reg));
+	return read16(acpimmio_gpio1 + reg);
 }
 
 static inline uint32_t gpio1_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_GPIO1_BASE + reg));
+	return read32(acpimmio_gpio1 + reg);
 }
 
 static inline void gpio1_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_GPIO1_BASE + reg), value);
+	write8(acpimmio_gpio1 + reg, value);
 }
 
 static inline void gpio1_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_GPIO1_BASE + reg), value);
+	write16(acpimmio_gpio1 + reg, value);
 }
 
 static inline void gpio1_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_GPIO1_BASE + reg), value);
+	write32(acpimmio_gpio1 + reg, value);
 }
 
 /* GPIO bank 2 */
 static inline uint8_t gpio2_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_GPIO2_BASE + reg));
+	return read8(acpimmio_gpio2 + reg);
 }
 
 static inline uint16_t gpio2_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_GPIO2_BASE + reg));
+	return read16(acpimmio_gpio2 + reg);
 }
 
 static inline uint32_t gpio2_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_GPIO2_BASE + reg));
+	return read32(acpimmio_gpio2 + reg);
 }
 
 static inline void gpio2_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_GPIO2_BASE + reg), value);
+	write8(acpimmio_gpio2 + reg, value);
 }
 
 static inline void gpio2_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_GPIO2_BASE + reg), value);
+	write16(acpimmio_gpio2 + reg, value);
 }
 
 static inline void gpio2_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_GPIO2_BASE + reg), value);
+	write32(acpimmio_gpio2 + reg, value);
 }
 
 static inline uint8_t xhci_pm_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg));
+	return read8(acpimmio_xhci_pm + reg);
 }
 
 static inline uint16_t xhci_pm_read16(uint8_t reg)
 {
-	return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg));
+	return read16(acpimmio_xhci_pm + reg);
 }
 
 static inline uint32_t xhci_pm_read32(uint8_t reg)
 {
-	return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg));
+	return read32(acpimmio_xhci_pm + reg);
 }
 
 static inline void xhci_pm_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
+	write8(acpimmio_xhci_pm + reg, value);
 }
 
 static inline void xhci_pm_write16(uint8_t reg, uint16_t value)
 {
-	write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
+	write16(acpimmio_xhci_pm + reg, value);
 }
 
 static inline void xhci_pm_write32(uint8_t reg, uint32_t value)
 {
-	write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
+	write32(acpimmio_xhci_pm + reg, value);
 }
 
 static inline uint8_t aoac_read8(uint8_t reg)
 {
-	return read8((void *)(ACPIMMIO_AOAC_BASE + reg));
+	return read8(acpimmio_aoac + reg);
 }
 
 static inline void aoac_write8(uint8_t reg, uint8_t value)
 {
-	write8((void *)(ACPIMMIO_AOAC_BASE + reg), value);
+	write8(acpimmio_aoac + reg, value);
 }
 
 #endif /* __AMDBLOCKS_ACPIMMIO_H__ */