soc/amd/gpio, mb/{amd,google}: Configure pads using a single entry in GPIO configuration table

Currently, for Stoneyridge and Picasso mainboards, pads that are
configured for SCI/SMI/WAKE need to have multiple entries in the
configuration table - one for PAD_GPI and other for the special
configuration that is required. This requires a very specific ordering
of pads within the table and is prone to errors because of conflicting
params provided to the different entries for the same pad. This also
does not work very well with the concept of override GPIOs where the
entry in base table is overridden with the first matched entry from
the override table.

This change updates the way GPIO configuration is handled for special
routing like SCI/SMI/WAKE/DEBOUNCE by setting the control field of
soc_amd_gpio structure in the macros performing these
configurations. Also, program_gpios() is updated to perform a write to
GPIO control register instead of read-modify-write. This is because
mainboard is expected to provide only a single configuration entry for
each pad within a given table. Thus, there is no need to preserve
earlier configuration.

Mainboards that were providing multiple entries for a single pad are
updated accordingly.

BUG=b:159944426

Change-Id: I3364dc2982d66c4e33c2b4e6b0b97641ebea27f0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 16 insertions, 56 deletions

diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index caf07c0192..883dcfa783 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -21,17 +21,6 @@ static int get_gpio_gevent(uint8_t gpio, const struct soc_amd_event *table,
 	return -1;
 }
 
-static void mem_read_write32(uint32_t *address, uint32_t value, uint32_t mask)
-{
-	uint32_t reg32;
-
-	value &= mask;
-	reg32 = read32(address);
-	reg32 &= ~mask;
-	reg32 |= value;
-	write32(address, reg32);
-}
-
 static void program_smi(uint32_t flags, int gevent_num)
 {
 	uint8_t level;
@@ -187,7 +176,6 @@ __weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {}
 
 void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
 {
-	uint32_t *gpio_ptr;
 	uint32_t control, control_flags;
 	uint8_t mux, index, gpio;
 	int gevent_num;
@@ -219,51 +207,23 @@ void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
 		iomux_read8(gpio); /* Flush posted write */
 
 		soc_gpio_hook(gpio, mux);
+		__gpio_setbits32(gpio, PAD_CFG_MASK, control);
+
+		if (control_flags == 0)
+			continue;
+
+		gevent_num = get_gpio_gevent(gpio, gev_tbl, gev_items);
+		if (gevent_num < 0) {
+			printk(BIOS_WARNING, "Warning: GPIO pin %d has no associated gevent!\n",
+			       gpio);
+			continue;
+		}
 
-		gpio_ptr = gpio_ctrl_ptr(gpio);
-
-		if (control_flags & GPIO_FLAG_SPECIAL_MASK) {
-			gevent_num = get_gpio_gevent(gpio, gev_tbl, gev_items);
-			if (gevent_num < 0) {
-				printk(BIOS_WARNING, "Warning: GPIO pin %d has"
-					" no associated gevent!\n", gpio);
-				continue;
-			}
-			switch (control_flags & GPIO_FLAG_SPECIAL_MASK) {
-			case GPIO_FLAG_DEBOUNCE:
-				mem_read_write32(gpio_ptr, control,
-						GPIO_DEBOUNCE_MASK);
-				break;
-			case GPIO_FLAG_WAKE:
-				mem_read_write32(gpio_ptr, control,
-						INT_WAKE_MASK);
-				break;
-			case GPIO_FLAG_INT:
-				mem_read_write32(gpio_ptr, control,
-						AMD_GPIO_CONTROL_MASK);
-				break;
-			case GPIO_FLAG_SMI:
-				mem_read_write32(gpio_ptr, control,
-						INT_SCI_SMI_MASK);
-
-				program_smi(control_flags, gevent_num);
-				break;
-			case GPIO_FLAG_SCI:
-				mem_read_write32(gpio_ptr, control,
-						INT_SCI_SMI_MASK);
-
-				fill_sci_trigger(control_flags, gevent_num, &sci_trigger_cfg);
-
-				soc_route_sci(gevent_num);
-				break;
-			default:
-				printk(BIOS_WARNING, "Error, flags 0x%08x\n",
-							control_flags);
-				break;
-			}
-		} else {
-			mem_read_write32(gpio_ptr, control,
-						AMD_GPIO_CONTROL_MASK);
+		if (control_flags & GPIO_FLAG_SMI) {
+			program_smi(control_flags, gevent_num);
+		} else if (control_flags & GPIO_FLAG_SCI) {
+			fill_sci_trigger(control_flags, gevent_num, &sci_trigger_cfg);
+			soc_route_sci(gevent_num);
 		}
 	}