soc/amd: factor out common AOAC device enable and status query functions

The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits
to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is
the default value after reset for those bits on both platforms.

Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

1 files changed, 32 insertions, 0 deletions

diff --git a/src/soc/amd/common/block/aoac/aoac.c b/src/soc/amd/common/block/aoac/aoac.c
new file mode 100644
index 0000000000..c5f161bfcb
--- /dev/null
+++ b/src/soc/amd/common/block/aoac/aoac.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/aoac.h>
+
+/* This initiates the power on sequence, but doesn't wait for the device to be powered on. */
+void power_on_aoac_device(unsigned int dev)
+{
+	uint8_t byte = aoac_read8(AOAC_DEV_D3_CTL(dev));
+	byte |= FCH_AOAC_PWR_ON_DEV;
+	byte &= ~FCH_AOAC_TARGET_DEVICE_STATE;
+	byte |= FCH_AOAC_D0_INITIALIZED;
+	aoac_write8(AOAC_DEV_D3_CTL(dev), byte);
+}
+
+void power_off_aoac_device(unsigned int dev)
+{
+	uint8_t byte = aoac_read8(AOAC_DEV_D3_CTL(dev));
+	byte &= ~FCH_AOAC_PWR_ON_DEV;
+	aoac_write8(AOAC_DEV_D3_CTL(dev), byte);
+}
+
+bool is_aoac_device_enabled(unsigned int dev)
+{
+	uint8_t byte = aoac_read8(AOAC_DEV_D3_STATE(dev));
+	byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE);
+	if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE))
+		return true;
+	else
+		return false;
+}