diff options
author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-03 10:20:44 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2019-06-06 18:50:44 +0000 |
commit | 3ce0360592f036ce586a49db84146d435a23e662 (patch) | |
tree | 20377cf7cd209a20354fa21f9d0c8655fabacb45 /src/soc/amd/common/block/acpi/acpi.c | |
parent | 6ab5ed3b66fc215d0d03b19ab02fdcf8613c7d09 (diff) |
soc/amd/common: Rework block/acpi
The halt.c file relies on the ACPI register block in the AcpiMmio
range. This register block is consistent across AMD device
generations, so to prepare for moving additional stoneyridge support
to this directory by changing the file name and add a Kconfig symbol
to control the build.
BUG=b:131682806
Change-Id: I2f7442dd78bced7f69b0416a8cd751291f82151f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/block/acpi/acpi.c')
-rw-r--r-- | src/soc/amd/common/block/acpi/acpi.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c new file mode 100644 index 0000000000..200b3c12f5 --- /dev/null +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> +#include <halt.h> + +void poweroff(void) +{ + acpi_write32(MMIO_ACPI_PM1_CNT_BLK, + (SLP_TYP_S5 << SLP_TYP_SHIFT) | SLP_EN); + + /* + * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM + * to transition to S5 state. If halt is called in SMM, then it prevents + * the SMI handler from being triggered and system never enters S5. + */ + if (!ENV_SMM) + halt(); +} |