diff options
author | Marc Jones <marcj303@gmail.com> | 2017-05-04 21:17:45 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-06-26 00:45:41 +0000 |
commit | 244848462def7075e0c812a2f71c408668cacfe4 (patch) | |
tree | fde926f45d478b36eaebfd1261886c973b803857 /src/soc/amd/common/amd_pci_util.h | |
parent | a0199d8e1a96d94828b31f77e0a29a282871a76a (diff) |
soc: Add AMD Stoney Ridge southbridge code
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/
Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops
Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/common/amd_pci_util.h')
-rw-r--r-- | src/soc/amd/common/amd_pci_util.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/soc/amd/common/amd_pci_util.h b/src/soc/amd/common/amd_pci_util.h new file mode 100644 index 0000000000..fd5f077af3 --- /dev/null +++ b/src/soc/amd/common/amd_pci_util.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AMD_PCI_UTIL_H +#define AMD_PCI_UTIL_H + +#include <stdint.h> +#include <amd_pci_int_defs.h> + +/* FCH index/data registers */ +#define PCI_INTR_INDEX 0xc00 +#define PCI_INTR_DATA 0xc01 + +struct pirq_struct { + u8 devfn; + u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ +}; + +extern const struct pirq_struct * pirq_data_ptr; +extern u32 pirq_data_size; +extern const u8 * intr_data_ptr; +extern const u8 * picr_data_ptr; + +u8 read_pci_int_idx(u8 index, int mode); +void write_pci_int_idx(u8 index, int mode, u8 data); +void write_pci_cfg_irqs(void); +void write_pci_int_table (void); + +#endif /* AMD_PCI_UTIL_H */ |