diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-11 16:00:22 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-16 22:30:19 +0000 |
| commit | 5c5f211b5b6e042637cf0256d2040ea66dadc8e9 (patch) | |
| tree | 65487541f9f5d0575e97017383b28cc3ef0a58c3 /src/soc/amd/common/acpi | |
| parent | 24d024ae24ae5f7ebd241c56ea149ade971fc663 (diff) | |
soc/amd: Move aoac.asl from picasso into common
I also removed the unnecessary #include in soc.asl.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifbd79871fd49b18f45d97f64ccd68fa96eaaebce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50572
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/common/acpi')
| -rw-r--r-- | src/soc/amd/common/acpi/aoac.asl | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/src/soc/amd/common/acpi/aoac.asl b/src/soc/amd/common/acpi/aoac.asl new file mode 100644 index 0000000000..d7523dfe23 --- /dev/null +++ b/src/soc/amd/common/acpi/aoac.asl @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define AOAC_DEVICE(DEV_ID, SX) \ + PowerResource(AOAC, SX, 0) { \ + OperationRegion (AOAC, SystemMemory, ACPIMMIO_BASE(AOAC) + 0x40 + (DEV_ID << 1), 2) \ + Field (AOAC, ByteAcc, NoLock, Preserve) { \ + /* \ + * Target Device State \ + * \ + * 0 = D0 - Uninitialized \ + * 1 = D0 - Initialized \ + * 2 = D1/D2/D3Hot \ + * 3 = D3Cold \ + * \ + * This field is only used to cut off register access. It does not \ + * control any power states. D3Cold is the only value that will \ + * cut off register access. All other values will allow register \ + * access and are purely informational. \ + */ \ + TDS, 2, \ +\ + DS, 1, /* Device State - Purely informational */ \ +\ + /* \ + * Power On Dev \ + * \ + * 1 = Perform hardware sequence to power on the device \ + * 0 = Perform hardware sequence to power off the device \ + * \ + * This register is only valid when Is Software Control = 0. \ + */ \ + POD, 1, \ +\ + /* Software Power On Reset B */ \ + SPRB, 1, \ + /* Software Ref Clock OK */ \ + SRCO, 1, \ + /* Software Reset B */ \ + SRB, 1, \ + /* \ + * Is Software Control \ + * \ + * 1 = Allow software to control Power On Reset B, \ + * Ref Clock OK, and Reset B. \ + * 0 = Hardware control \ + */ \ + ISWC, 1, \ +\ + /* Power Reset B State */ \ + PRBS, 1, \ + /* Ref Clock OK State */ \ + RCOS, 1, \ + /* Reset B State */ \ + RBS, 1, \ + /* Device Off Gating State */ \ + DOGS, 1, \ + /* D3 Cold State */ \ + D3CS, 1, \ + /* Device Clock OK State */ \ + COS, 1, \ + /* State of device */ \ + STA0, 1, \ + /* State of device */ \ + STA1, 1, \ + } \ + Method(_STA) { \ + Local0 = (PRBS && RCOS && RBS) \ +\ + If (Local0) { \ + Return (1) \ + } Else { \ + Return (0) \ + } \ + } \ + Method(_ON, 0, Serialized) { \ + ISWC=0 \ + POD=1 \ +\ + While (!PRBS || !RCOS || !RBS) { \ + Stall (100) \ + } \ + } \ + Method(_OFF, 0, Serialized) { \ + ISWC=0 \ + POD=0 \ +\ + While (PRBS || RCOS || RBS) { \ + Stall (100) \ + } \ + } \ + Method(_RST, 0, Serialized) { \ + ISWC=1 \ + SRB=1 \ +\ + /* Assert the SwRstB signal for 200 us */ \ + Stall (200) \ +\ + SRB=0 \ + ISWC=0 \ +\ + While (!PRBS || !RCOS || !RBS) { \ + Printf ("Waiting for device to complete reset") \ + Stall (100) \ + } \ + } \ + } \ + Name (_PR0, Package () { AOAC }) \ + Name (_PR2, Package () { AOAC }) \ + Name (_PR3, Package () { AOAC }) \ + Method (_PS0, 0, Serialized) { \ + ^AOAC.TDS = 1 \ + } \ + Method (_PS3, 0, Serialized) { \ + ^AOAC.TDS = 3 \ + } |