soc/amd/picasso: Add STXS and CTXS method

Add STXS and CTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.

BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48943
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 31 insertions, 0 deletions

diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl
index 9686ddc1c9..f209f448c1 100644
--- a/src/soc/amd/common/acpi/gpio_bank_lib.asl
+++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl
@@ -2,6 +2,9 @@
 
 #include <soc/iomap.h>
 
+#define GPIO_OUTPUT_SHIFT	22
+#define GPIO_OUTPUT_VALUE	(1 << GPIO_OUTPUT_SHIFT)
+
 /* Get pin control MMIO address */
 Method (GPAD, 0x1)
 {
@@ -117,3 +120,31 @@ Method (GPW3, 0x2)
 	/* Arg1 - Value for control register */
 	GPSB (Arg0, 3, Arg1)
 }
+
+/*
+ * Set GPIO Output Value
+ * Arg0 - GPIO Number
+ */
+Method (STXS, 1, Serialized)
+{
+	OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+	VAL0 |= GPIO_OUTPUT_VALUE
+}
+
+/*
+ * Clear GPIO Output Value
+ * Arg0 - GPIO Number
+ */
+Method (CTXS, 1, Serialized)
+{
+	OperationRegion (GPDW, SystemMemory, GPAD (Arg0), 4)
+	Field (GPDW, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+	VAL0 &= ~GPIO_OUTPUT_VALUE
+}