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| author | Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> | 2023-05-16 17:30:23 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-01 13:09:40 +0000 |
| commit | e811c9a44d04bec211f111f73e47f4d3be9d2117 (patch) | |
| tree | 866a5aeaebb786bbc7cd6c52aae9a13a7daecdf9 /src/soc/amd/cezanne | |
| parent | 44b60eb503778c1a39785963006112aa6cfc8ddd (diff) | |
mb/google/corsola: Fix MIPI panel power on/off sequence
Based on the power sequence of the panel [1] and PMIC datasheet [2],
the power on T2 sequence VSP to VSN should be large than 1ms, but it's
-159us now, and the power off T2 sequence VSP to VSN should be large
than 0ms, but it's less than 0 now. Let's modify the power sequence
to meet the datasheet requirement.
[1] HX83102-J02_Datasheet_v03.pdf
[2] TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf
BUG=b:282902297
TEST=power sequence T2 pass
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Ib1625c6a211f849071393f69eaf5c649a8e7f72e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75298
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne')
0 files changed, 0 insertions, 0 deletions