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authorArthur Heymans <arthur@aheymans.xyz>2022-05-31 21:48:15 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-09-14 20:29:17 +0000
commite48dcb708c97923f39762ab60ad0423767e2b84c (patch)
treecbbd63d0efdcc85104b34fc94028b600a569d6c1 /src/soc/amd/cezanne
parent44807acaefc71cd4985779e742e6791cb9daf65d (diff)
cpu/amd/smm: Move MP & SMM init in a common place
Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64870 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne')
-rw-r--r--src/soc/amd/cezanne/cpu.c35
1 files changed, 3 insertions, 32 deletions
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index 8b4e347331..8c15b55c40 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -1,57 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h>
#include <amdblocks/cpu.h>
#include <amdblocks/iomap.h>
#include <amdblocks/mca.h>
-#include <amdblocks/reset.h>
-#include <amdblocks/smm.h>
#include <assert.h>
#include <console/console.h>
#include <cpu/amd/microcode.h>
-#include <cpu/amd/mtrr.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
-#include <cpu/x86/smm.h>
-#include <acpi/acpi.h>
#include <device/device.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
-#include <types.h>
_Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of "
"available cores, use the downcore_mode and disable_smt devicetree settings instead.");
/* MP and SMM loading initialization */
-/*
- * Do essential initialization tasks before APs can be fired up -
- *
- * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
- * creates the MTRR solution that the APs will use. Otherwise APs will try to
- * apply the incomplete solution as the BSP is calculating it.
- */
-static void pre_mp_init(void)
-{
- const msr_t syscfg = rdmsr(SYSCFG_MSR);
- if (syscfg.lo & SYSCFG_MSR_TOM2WB)
- x86_setup_mtrrs_with_detect_no_above_4gb();
- else
- x86_setup_mtrrs_with_detect();
- x86_mtrr_check();
-}
-
-static const struct mp_ops mp_ops = {
- .pre_mp_init = pre_mp_init,
- .get_cpu_count = get_cpu_count,
- .get_smm_info = get_smm_info,
- .relocation_handler = smm_relocation_handler,
- .post_mp_init = global_smi_enable,
-};
-
void mp_init_cpus(struct bus *cpu_bus)
{
- if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
+ extern const struct mp_ops amd_mp_ops_with_smm;
+ if (mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm) != CB_SUCCESS)
die_with_post_code(POST_HW_INIT_FAILURE,
"mp_init_with_smm failed. Halting.\n");